Naveed A. Sherwani

Naveed A. Sherwani: Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs. DFT 2009: 123-123

Naveed A. Sherwani, Susan Lippincott Mack, Alex Alexanian, Premal Buch, Carlo Guardiani, Harold Lehon, Peter Rabkin, Atul Sharan: DFM rules! DAC 2005: 168-169

Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani: Integrated floorplanning with buffer/channel insertion for bus-based designs. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 730-741 (2003)

Robert Dahlberg, Shishpal Rawat, Jen Bernier, Gina Gloski, Aurangzeb Khan, Kaushik Patel, Paul Ruddy, Naveed A. Sherwani, Ronnie Vasishta: COT - customer owned trouble. DAC 2003: 91-92

Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani: Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. ISPD 2002: 56-61

T. Karn, Shishpal Rawat, Desmond Kirkpatrick, Rabindra K. Roy, Greg Spirakis, Naveed A. Sherwani, Craig Peterson: EDA challenges facing future microprocessor design. IEEE Trans. on CAD of Integrated Circuits and Systems 19(12): 1498-1506 (2000)

Dinesh P. Mehta, Naveed A. Sherwani: On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs. ACM Trans. Design Autom. Electr. Syst. 5(1): 82-97 (2000)

Naveed A. Sherwani: The bottom-10 problems in EDA (panel session (title only)). ISPD 2000: 39

Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani: Integrated floorplanning and interconnect planning. ICCAD 1999: 354-357

Jeff Parkhurst, Naveed A. Sherwani, Sury Maturi, Dana Ahrams, Eli Chiprout: SRC physical design top ten problem. ISPD 1999: 55-58

Naveed A. Sherwani, Prashant Sawkar: Embedded Tutorial: Layout Driven Synthesis or Synthesis Driven Layout. VLSI Design 1998: 44-47

Dinesh P. Mehta, Naveed A. Sherwani, A. Bariya: T3: Physical Design. VLSI Design 1997: 3-

Srinivasa R. Danda, Xiaolin Liu, Sreekrishna Madhwapathy, Anand Panyam, Naveed A. Sherwani, Ioannis G. Tollis: Optimal algorithms for planar over-the-cell routing problems. IEEE Trans. on CAD of Integrated Circuits and Systems 15(11): 1365-1378 (1996)

Dinesh P. Mehta, Naveed A. Sherwani: A Minimum-Area Floorplanning Algorithm for MBC Designs. Great Lakes Symposium on VLSI 1996: 56-59

Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani, A. Sureka: OPRON: a new approach to planar OTC routing. Great Lakes Symposium on VLSI 1995: 208-212

Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani: Optimal algorithms for planar over-the-cell routing in the presence of obstacles. VLSI Design 1995: 3-7

Alfred J. Boals, Ajay K. Gupta, Naveed A. Sherwani: Incomplete hypercubes: Algorithms and embeddings. The Journal of Supercomputing 8(3): 263-294 (1994)

Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam: A Unified Approach to Multilayer Over-the-Cell Routing. DAC 1994: 182-187

Qiong Yu, Sandeep Badida, Naveed A. Sherwani: Algorithmic Aspects of Three Dimensional MCM Routing. DAC 1994: 397-401

Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam: An Efficient Four Layer Over-the-Cell Router. ISCAS 1994: 187-190

Pramod Anne, Aditya Reddy, Naveed A. Sherwani, Anand Panyam, Siddharth Bhingarde: Comparative Analysis of New CMOS Leaf Cells for OTC Routing. ISCAS 1994: 191-194

Wasim Khan, Sreekrishna Madhwapathy, Naveed A. Sherwani: A Hierarchical Approach to Clock Routing in High Performance Systems. ISCAS 1994: 467-470

Jim E. Crenshaw, Spyros Tragoudas, Naveed A. Sherwani: High Performance Over-the-Cell Routing. VLSI Design 1994: 137-142

Siddharth Bhingarde, Rafay Khawaja, Anand Panyam, Naveed A. Sherwani: Over-the-Cell Routing Algorithms for Industrial Cell Models. VLSI Design 1994: 143-148

Naveed A. Sherwani: Algorithms for VLSI physical design automation. Kluwer 1993, isbn 978-0-7923-9294-1, pp. I-XXIV, 1-488

Dana L. Grinstead, Peter J. Slater, Naveed A. Sherwani, Nancy D. Holmes: Efficient Edge Domination Problems in Graphs. Inf. Process. Lett. 48(5): 221-228 (1993)

Jason Cong, Moazzem Hossain, Naveed A. Sherwani: A provably good multilayer topological planar routing algorithm in IC layout designs. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 70-78 (1993)

Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh: Utilization of vacant terminals for improved over-the-cell channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 12(6): 780-792 (1993)

Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani: Middle terminal cell models for efficient over-the-cell routing in high-performance circuits. IEEE Trans. VLSI Syst. 1(4): 462-472 (1993)

Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani: Efficient Over-the-cell Routing Algorithm for General Middle Terminal Model. ISCAS 1993: 1861-1864

Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani: On Optimum Cell Models for Over-the-Cell Routing. VLSI Design 1993: 94-99

Jason Cong, Moazzem Hossain, Naveed A. Sherwani: A Provably Good Algorithm for k-Layer Topological Planar Routing Problems. VLSI Design 1993: 113

Sivakumar Natarajan, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh: Over-the-Cell Channel Routing for High Performance Circuits. DAC 1992: 600-603

Bo Wu, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh: Over-the-Cell Routers for New Cell Model. DAC 1992: 604-607

Surendra Burman, Chandar Kamalanathan, Naveed A. Sherwani: New channel segmentation model and associated routing algorithm for high performance FPGAs. ICCAD 1992: 22-25

Wasim Khan, Moazzem Hossain, Naveed A. Sherwani: Zero skew clock routing in multiple-clock synchronous systems. ICCAD 1992: 464-467

Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh: New Algorithm for Over-the-Cell Channel Routing Using Vacant Terminals. DAC 1991: 126-131

Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh: Algorithms for Three-Layer Over-The-Cell Channel Routing. ICCAD 1991: 428-431

Moazzem Hossain, Naveed A. Sherwani: On Topological Via Minimization and Routing. ICCAD 1991: 532-535

S. Miriyala, Jahangir A. Hashmi, Naveed A. Sherwani: Switchbox Steiner Tree Problem in Presence of Obstacles. ICCAD 1991: 536-539

Alfred J. Boals, Ajay K. Gupta, Jahangir A. Hashmi, Naveed A. Sherwani: Compact Hypercubes: Properties and Recognition. ICCI 1991: 395-402

Alfred J. Boals, Ajay K. Gupta, Jahangir A. Hashmi, Naveed A. Sherwani: An Efficient Approximation Algorithm for Hypercube Scheduling. ICCI 1991: 474-483

Venkata K. Prabhala, Naveed A. Sherwani: Fully Normal Algorithms for Incomplete Hypercubes. IPPS 1991: 144-150

Ajay K. Gupta, Alfred J. Boals, Naveed A. Sherwani: On Optimal Embeddings into Incomplete Hypercubes. IPPS 1991: 416-423

Naveed A. Sherwani, Elise de Doncker, John A. Kapenga (Eds.): Computing in the 90's, The First Great Lakes Computer Science Conference, Kalamazzo, Michigan, USA, October 18-20, 1989, Proceedings. Lecture Notes in Computer Science 507, Springer 1991, isbn 3-540-97628-0

Roshan A. Gidwani, Naveed A. Sherwani: MISER: An Integrated Three Layer Gridless Channel Router and Compactor. DAC 1990: 698-703

Naveed A. Sherwani, Jitender S. Deogun: A New Heuristic for Single Row Routing Problems. DAC 1989: 167-172