- CSB - MetaPress - Google - Bing - Yahoo
 | 2002 | |
|---|---|---|
| c18 |      | Yoondong Park, Steve H. Jen, Bing J. Sheu, Heesook Yoon, In Gyeom Kim: An efficient parameter extraction method using statistical optimization in S-CMOS deep-submicron/nanometer model. ISCAS (5) 2002: 233-236 |
| 2001 | ||
| c17 | | Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang: Panel: Is Nanometer Design Under Control? DAC 2001: 591-592 |
| 2000 | ||
| c16 | | Yoondong Park, Jim-Shih Liaw, Theodore W. Berger, Bing J. Sheu: Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses. IJCNN (4) 2000: 214-218 |
| 1998 | ||
| j18 | | Steve H. Jen, Bing J. Sheu: A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 169-172 (1998) |
| 1997 | ||
| j17 | | Bing J. Sheu, Mohammed Ghanbari, Horng-Dar Lin, Chung-Yu Wu: Guest Editorial. IEEE Trans. Circuits Syst. Video Techn. 7(4): 571-574 (1997) |
| j16 | | David Cheng-Hsiung Chen, Bing J. Sheu, Wayne C. Young: A CDMA communication detector with robust near-far resistance using paralleled array processors. IEEE Trans. Circuits Syst. Video Techn. 7(4): 654-662 (1997) |
| j15 | | Richard H. Tsai, Bing J. Sheu, Andrew Kostrzewski, Jeongdal Kim: Advances in efficient optical links to enhance desktop multimedia processor systems. IEEE Trans. Circuits Syst. Video Techn. 7(4): 707-713 (1997) |
| c15 |  | Wai-Chi Fang, Guang Yang, Bedabrata Pain, Bing J. Sheu: A Low Power Smart Vision System Based on Active Pixel Sensor Integrated with Programmable Neural Processor. ICCD 1997: 429-434 |
| 1996 | ||
| j14 | | Sa Hyun Bang, Bing J. Sheu, Tony H. Wu: Optimal solutions for cellular neural networks by paralleled hardware annealing. IEEE Trans. Neural Netw. Learning Syst. 7(2): 440-454 (1996) |
| c14 | | David C. Chen, Bing J. Sheu, Theodore W. Berger: A Compact Neural Network Based CDMA Receiver for Multimedia Wireless Communication. ICCD 1996: 99- |
| 1995 | ||
| c13 | | Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang: VLSI design of densely-connected array processors. ICCD 1995: 492-497 |
| c12 | | Wai-Chi Fang, Bing J. Sheu, Holger Venus, Rainer Sandau: Smart-pixel array processors based on optimal cellular neural networks for space sensor applications. ICCD 1995: 703- |
| c11 | | Bing J. Sheu, Sa Hyun Bang, Wai-Chi Fang: VLSI Design of Cellular Neutral Networks with Annealing and Optical Input Capabilities. ISCAS 1995: 653-656 |
| c10 | | Bing J. Sheu, Robert C. Chang, Tony H. Wu, Sa Hyun Bang: VLSI-Compatible Cellular Neural Networks with Optimal Solution Capability for Optimization. ISCAS 1995: 1165-1168 |
| c9 | | Bing J. Sheu, Theodore W. Berger, Tony H. Wu, Richard H. Tsai: VLSI Neural Network Implementation of a Hippocampal Model. ISCAS 1995: 1664-1667 |
| c8 | | Bing J. Sheu: Constructing Intelligent Microsystems with Modular VLSI Networks Design. ISCAS 1995: 2100-2103 |
| 1994 | ||
| j13 | | Sudhir M. Gowda, Bing J. Sheu: BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1166-1170 (1994) |
| j12 | | Oscal T.-C. Chen, Bing J. Sheu, Zhen Zhang: An adaptive vector quantizer based on the Gold-Washing method for image compression. IEEE Trans. Circuits Syst. Video Techn. 4(2): 143-157 (1994) |
| j11 | | Oscal T.-C. Chen, Bing J. Sheu, Wai-Chi Fang: Image compression using self-organization networks. IEEE Trans. Circuits Syst. Video Techn. 4(5): 480-489 (1994) |
| j10 | | Wai-Chi Fang, Chi-Yung Chang, Bing J. Sheu, Oscal T.-C. Chen, J. C. Curlander: VLSI systolic binary tree-searched vector quantizer for image compression. IEEE Trans. VLSI Syst. 2(1): 33-44 (1994) |
| j9 | | Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang: A Gaussian synapse circuit for analog VLSI neural networks. IEEE Trans. VLSI Syst. 2(1): 129-133 (1994) |
| j8 | | Sudhir M. Gowda, Bing J. Sheu, Wen-Jay Hsu: Testing of programmable analog neural network chips. VLSI Signal Processing 8(3): 267-282 (1994) |
| c7 | | Robert C.-H. Chang, Bing J. Sheu: An Analog MOS Model for Circuit Simulation and Benchmark Test Results. ISCAS 1994: 311-314 |
| c6 | | Sa Hyun Bang, Bing J. Sheu, Josephine C.-F. Chang: Search of Optimal Solutions in Multi-Level Neural Networks. ISCAS 1994: 423-426 |
| c5 | | Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang: A Gaussian Synapse Circuit for Analog VLSI Neural Networks. ISCAS 1994: 483-486 |
| 1993 | ||
| j7 | | Ji-Chien Lee, Bing J. Sheu, Rama Chellappa: A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture. VLSI Signal Processing 5(2-3): 185-199 (1993) |
| j6 | | Ji-Chien Lee, Bing J. Sheu, Rama Chellappa: A mixed-signal VLSI competitive neuroprocessor for video motion detection. VLSI Signal Processing 6(1): 57-66 (1993) |
| 1992 | ||
| j5 | | Oscal T.-C. Chen, Bing J. Sheu, Wai-Chi Fang: Image Compression on a VLSI Neural-Based Vector Quantizer. Inf. Process. Manage. 28(6): 687-706 (1992) |
| j4 | | Ji-Chien Lee, Bing J. Sheu, Joongho Choi, Ramalingam Chellappa: A mixed-signal VLSI neuroprocessor for image restoration. IEEE Trans. Circuits Syst. Video Techn. 2(3): 319-324 (1992) |
| c4 | | Oscal T.-C. Chen, Z. Zhang, Bing J. Sheu: An Adaptive High-Speed Lossy Data Compression. Data Compression Conference 1992: 349-358 |
| 1991 | ||
| c3 | | Wai-Chi Fang, Bing J. Sheu, Oscal T.-C. Chen: A Neural Network Based VLSI Vector Quantizer for Real-Time Image Compression. Data Compression Conference 1991: 342-351 |
| c2 | | Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda: Testing of Analog Neural Array-Processor Chips. ICCD 1991: 118-121 |
| c1 | | Joongho Choi, Bing J. Sheu: A GaAs Receiver Module for Optoelectronic Computing and Interconnection. ICCD 1991: 494-497 |
| 1988 | ||
| j3 | | Bing J. Sheu, Wen-Jay Hsu, P. K. Ko: An MOS transistor charge model for VLSI design. IEEE Trans. on CAD of Integrated Circuits and Systems 7(4): 520-527 (1988) |
| j2 | | Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu: Device and circuit simulation interface for an integrated VLSI design environment. IEEE Trans. on CAD of Integrated Circuits and Systems 7(9): 998-1004 (1988) |
| 1987 | ||
| j1 | | M. C. Hsu, Bing J. Sheu: Inverse-Geometry Dependence of MOS Transistor Electrical Parameters. IEEE Trans. on CAD of Integrated Circuits and Systems 6(4): 582-585 (1987) |
Colors in the list of coauthors
Last update Thu May 23 05:21:58 2013 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page