Ming-Hwa Sheu

Wen-Kai Tsai, Ming-Hwa Sheu, Chung-Chi Lin: Block-Based Major Color Method for Foreground Object Detection on Embedded SoC Platforms. Embedded Systems Letters 4(2): 49-52 (2012)

Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu: Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme. IEEE Trans. VLSI Syst. 20(2): 361-366 (2012)

Wen-Kai Tsai, Ming-Hwa Sheu, Chung-Chi Lin: Region-Based Background Subtraction for Complex Sense on Embedded Platforms. IIH-MSP 2012: 351-354

Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu: Low power 10-transistor full adder design based on degenerate pass transistor logic. ISCAS 2012: 496-499

Wen-Kai Tsai, Ming-Hwa Sheu, Chung-Chi Lin, Ho-En Liao: A robust background modeling and foreground object detection using color component analysis. SMC 2012: 263-267

Chung-Chi Lin, Wen-Kai Tsai, Ming-Hwa Sheu: A hybrid pixel-based background model for image foreground object detection in complex sence. TSP 2012: 720-724

Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu: A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits. IEICE Transactions 93-A(4): 843-845 (2010)

Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu: Low Power Pulse Generator Design Using Hybrid Logic. IEICE Transactions 93-A(6): 1266-1268 (2010)

Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu: A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic. IEICE Transactions 93-A(12): 2755-2757 (2010)

Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Zeng-Chuan Wu, Wen-Kai Tsai: An Efficient Architecture of Extended Linear Interpolation for Image Processing. J. Inf. Sci. Eng. 26(2): 631-648 (2010)

Chung-Chi Lin, Ming-Hwa Sheu, Chishyan Liaw, Huann-Keng Chiang: Fast First-Order Polynomials Convolution Interpolation for Real-Time Digital Image Reconstruction. IEEE Trans. Circuits Syst. Video Techn. 20(9): 1260-1264 (2010)

Ming-Hwa Sheu, Wen-Kai Tsai, Chuang-Chun Hu, Chun-Heng Tsao: Fast Texture-Based Object Tracking Algorithm on Embedded Platform. FCST 2010: 511-514

Wen-Kai Tsai, Ming-Hwa Sheu, Chung-Chi Lin: Efficient Multi-Layer Background Model on Complex Environment for Foreground Object Detection. IIH-MSP 2010: 292-295

Shyue-Wen Yang, Ming-Hwa Sheu, Jun-Jie Lin, Chuang-Chun Hu, Tzu-Hsiung Chen, Shau-Yin Tseng: Parallel 3-Pixel Labeling Method and its Hardware Architecture Design. IAS 2009: 185-188

Wen-Kai Tsai, Ming-Hwa Sheu, Ching-Lung Su, Jun-Jie Lin, Shau-Yin Tseng: Image Object Detection and Tracking Implementation for Outdoor Scenes on an Embedded Soc Platform. IIH-MSP 2009: 386-389

Yuan-Ching Kuo, Su-Hon Lin, Ming-Hwa Sheu, Jia-You Wu, Peng-Siang Wang: Efficient VLSI Design of a Reverse RNS Converter for New Flexible 4-Moduli Set (2^p+k, 2^p+1, 2^p-1, 2^2p+1). ISCAS 2009: 437-440

Su-Hon Lin, Ming-Hwa Sheu: Area-Time Efficient Modulo 2ⁿ - 1 Adder Design Using Hybrid Carry Selection. IEICE Transactions 91-D(2): 361-362 (2008)

Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu: Low Complexity Dual-Mode Pulse Generator Designs. IEICE Transactions 91-A(7): 1812-1815 (2008)

Su-Hon Lin, Ming-Hwa Sheu, Chao-Hsiang Wang: Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2ⁿ, 2ⁿ⁺¹ - 1, 2ⁿ - 1). IEICE Transactions 91-D(7): 2058-2060 (2008)

Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw: High-performance very large scale integration architecture design for various-ratio image scaling. J. Electronic Imaging 17(4): 043010 (2008)

Su-Hon Lin, Ming-Hwa Sheu: VLSI Design of Diminished-One Modulo 2ⁿ+1 Adder Using Circular Carry Selection. IEEE Trans. on Circuits and Systems 55-II(9): 897-901 (2008)

Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Wen-Kai Tsai, Zeng-Chuan Wu: Real-time FPGA architecture of extended linear convolution for digital image scaling. FPT 2008: 381-384

Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Zeng-Chuan Wu, Jia-Yi Tu, Chia-Hung Chen: A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing. ICESS 2008: 196-202

Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Zeng-Chuan Wu: The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing. ISCAS 2008: 480-483

Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chih-Jen Wei, Chishyan Liaw: A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information. IEICE Transactions 90-A(11): 2575-2583 (2007)

Chung-Chi Lin, Zeng-Chuan Wu, Wen-Kai Tsai, Ming-Hwa Sheu, Huann-Keng Chiang: The VLSI Design of Winscale for Digital Image Scaling. IIH-MSP 2007: 511-514

Shyue-Wen Yang, Ming-Hwa Sheu, Chun-Kai Yeh, Chih-Yuen Wen, Chih-Chieh Lin, Wen-Kai Tsai: Fast Fair Crossbar Scheduler for On-chip Router. ISCAS 2007: 385-388

Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu: Low Power Multipliers Using Enhenced Row Bypassing Schemes. SiPS 2007: 136-141

Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, Si-Ying Chen: Efficient VLSI Design of Modulo 2ⁿ-1 Adder Using Hybrid Carry Selection. SiPS 2007: 142-145

Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu: Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. APCCAS 2006: 594-597

Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chih-Jen Wei: The VLSI Design of Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection. APCCAS 2006: 1587-1590

Su-Hon Lin, Ming-Hwa Sheu, Jing-Shiun Lin, Wen-Tsai Sheu: Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1). APCCAS 2006: 2020-2023

Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Ming-che Chen: Film-to-Video Conversion with Scene Cut Detection. ICICIC (1) 2006: 285-289

Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho: A high speed and energy efficient full adder design using complementary & level restoring carry logic. ISCAS 2006

Chung-Chi Lin, Chih-Jen Wei, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw: The VLSI design of de-interlacing with scene change detection. ISCAS 2006

Yin-Tsung Hwang, Jiun-Yan Chen, Ming-Hwa Sheu: Automatic Generation of Programmable Parallel CRC & Scrambler Designs. SiPS 2006: 286-291

Shyue-Wen Yang, Ming-Hwa Sheu, Hsien-Huang P. Wu, Hung-En Chien, Ping-Kuo Weng, Ying-Yih Wu: VLSI architecture design for a fast parallel label assignment in binary image. ISCAS (3) 2005: 2393-2396

Hsien-Huang P. Wu, Ming-Hwa Sheu, Tung-Yu Yang: Directional interpolation for field-sequential stereoscopic video. ISCAS (3) 2005: 2879-2882

Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw: Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection. PCM (1) 2005: 291-302

Chichyang Chen, Rui-Lin Chen, Ming-Hwa Sheu: A Fast Additive Normalization Method for Exponential Computation. DSD 2003: 286-293

Ming-Hwa Sheu, Su-Hon Lin: Fast design approach for implementing the approximate squaring function. APCCAS (2) 2002: 25-29

Ming-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen, Hsin-Fu Lo: A Systematic Approach for Parallel CRC Computations. J. Inf. Sci. Eng. 17(3): 445-461 (2001)

Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu: VLSI architecture of extended in-place path metric update for Viterbi decoders. ISCAS (4) 2001: 206-209

Ming-Hwa Sheu, Ho-En Liao, Shih Tsung Kan, Ming-Der Shieh: A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. ISCAS (4) 2001: 446-449

Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu: High-speed generation of LFSR signatures. Asian Test Symposium 2000: 222-

Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu: A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. ISCAS (1) 1999: 500-503

Ming-Hwa Sheu, Yuan-Long Jeang, Jhing-Fa Wang, Jau-Yien Lee: The determination of the cycle length in high level synthesis. Integration 16(2): 131-148 (1993)

Ming-Hwa Sheu, Jhing-Fa Wang, Jau-Yien Lee, Lian-Ying Liu: An Expandable Chip Desing for Gray-scale Morphological Operations. ISCAS 1993: 1563-1566

Ming-Hwa Sheu, Jau-Yien Lee, Jhing-Fa Wang, An-Nan Suen, Lian-Ying Liu: A High Throughput-Rate Architecture for 8*8 2-D DCT. ISCAS 1993: 1578-1590