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Junhao Shi
2010 – today
- 2011
[c7]Junhao Shi, Mingmin Zhang, Zhigeng Pan: A real-time bimanual 3D interaction method based on bare-hand tracking. ACM Multimedia 2011: 1073-1076
2000 – 2009
- 2006
- [c6]Görschwin Fey, Junhao Shi, Rolf Drechsler: Efficiency of Multi-Valued Encoding in SAT-based ATPG. ISMVL 2006: 25
- 2005
- [c5]Junhao Shi, Görschwin Fey, Rolf Drechsler: Bridging fault testability of BDD circuits. ASP-DAC 2005: 188-191
- [c4]Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. ISVLSI 2005: 212-217
- 2004
- [j1]Rolf Drechsler, Junhao Shi, Görschwin Fey: Synthesis of fully testable circuits from BDDs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 440-443 (2004)
- [c3]Görschwin Fey, Junhao Shi, Rolf Drechsler: BDD Circuit Optimization for Path Delay Fault Testability. DSD 2004: 168-172
- 2003
- [c2]Junhao Shi, Görschwin Fey, Rolf Drechsler: BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. Asian Test Symposium 2003: 290-293
- [c1]Rolf Drechsler, Junhao Shi, Görschwin Fey: MuTaTe: an efficient design for testability technique for multiplexor based circuits. ACM Great Lakes Symposium on VLSI 2003: 80-83
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last updated on 2012-12-02 20:27 CET by the dblp team