| 2013 | ||
|---|---|---|
| j24 | Shanthi Pavan, Wouter A. Serdijn, Henry Shu-Hung Chung, Ming-Der Shieh, Young Hwan Kim: Guest Editorial Special Section on the 2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012). IEEE Trans. on Circuits and Systems 60-I(5): 1101-1103 (2013) | |
| 2012 | ||
| j23 | Ming-Der Shieh, Shih-Hao Fang, Shing-Chung Tang, Der-Wei Yang: Low-Complexity Memory Access Architectures for Quasi-Cyclic LDPC Decoders. IEICE Transactions 95-D(2): 549-557 (2012) | |
| j22 | Ming-Der Shieh, Yin-Tsung Hwang, Hanho Lee, Chirn Chye Boon, Zhiyuan Yan: Implementations of Signal-Processing Algorithms for OFDM Systems. J. Electrical and Computer Engineering 2012 (2012) | |
| c38 | Shih-Hao Fang, Ju-Ya Chen, Jing-Shiun Lin, Ming-Der Shieh, Wei-Chieh Huang, Jen-Yuan Hsu: Blind channel estimation for MIMO-OFDM systems with repeated time-domain symbols. APCCAS 2012: 37-40 | |
| c37 | Der-Wei Yang, Chun-Wei Chen, Che-Hao Chang, Yun-Chen Chang, Ming-Der Shieh, Jonas Wang, Chia-Cheng Lo: Face detection architecture design using hybrid skin color detection and cascade of classifiers. APCCAS 2012: 543-546 | |
| c36 | Wen-Ching Lin, Jheng-Hao Ye, Der-Wei Yang, Si-Yu Huang, Ming-Der Shieh, Jonas Wang: Efficient scissoring scheme for scanline-based rendering of 2D vector graphics. ISCAS 2012: 766-769 | |
| c35 | Jing-Shiun Lin, Yin-Tsung Hwang, Po-Han Chu, Ming-Der Shieh, Shih-Hao Fang: An efficient QR decomposition design for MIMO systems. ISCAS 2012: 1508-1511 | |
| c34 | Sheng-Hong Wang, Wen-Ching Lin, Jheng-Hao Ye, Ming-Der Shieh: Fast scalable radix-4 Montgomery modular multiplier. ISCAS 2012: 3049-3052 | |
| 2011 | ||
| j21 | Chin-Long Wey, Shin-Yo Lin, Pei-Yun Tsai, Ming-Der Shieh: Reconfigurable Homogenous Multi-Core FFT Processor Architectures for Hybrid SISO/MIMO OFDM Wireless Communications. IEICE Transactions 94-A(7): 1530-1539 (2011) | |
| j20 | Ming-Der Shieh, Yung-Kuei Lu: Design and Implementation of a Low-Complexity Reed-Solomon Decoder for Optical Communication Systems. IEICE Transactions 94-D(8): 1557-1564 (2011) | |
| j19 | Ming-Der Shieh, Wen-Ching Lin, Chien-Ming Wu: Design of High-Speed Iterative Dividers in GF(2m). J. Inf. Sci. Eng. 27(3): 953-967 (2011) | |
| c33 | Ming-Der Shieh, Shih-Hao Fang, Shing-Chung Tang, Der-Wei Yang: VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes. SoCC 2011: 242-246 | |
| 2010 | ||
| j18 | Shih-Hao Fang, Ju-Ya Chen, Ming-Der Shieh, Jing-Shiun Lin: Blind Channel Estimation for SIMO-OFDM Systems without Cyclic Prefix. IEICE Transactions 93-A(1): 339-343 (2010) | |
| j17 | Yung-Kuei Lu, Ming-Der Shieh: High-Speed Low-Complexity Architecture for Reed-Solomon Decoders. IEICE Transactions 93-D(7): 1824-1831 (2010) | |
| j16 | Ming-Der Shieh, Wen-Ching Lin: Word-Based Montgomery Modular Multiplication Algorithm for Low-Latency Scalable Architectures. IEEE Trans. Computers 59(8): 1145-1151 (2010) | |
| j15 | Chia-Cheng Lo, Shang-Ta Tsai, Ming-Der Shieh: Reconfigurable architecture for entropy decoding and inverse transform in H.264. IEEE Trans. Consumer Electronics 56(3): 1670-1676 (2010) | |
| j14 | Shin-Yo Lin, Chin-Long Wey, Ming-Der Shieh: Low-cost FFT processor for DVB-T2 applications. IEEE Trans. Consumer Electronics 56(4): 2072-2079 (2010) | |
| j13 | Jun-Hong Chen, Ming-Der Shieh, Wen-Ching Lin: A High-Performance Unified-Field Reconfigurable Cryptographic Processor. IEEE Trans. VLSI Syst. 18(8): 1145-1158 (2010) | |
| c32 | Chia-Cheng Lo, Chia-Wei Hsu, Ming-Der Shieh: Area-Efficient H.264 VLC Decoder Using Sub-tree Classification. IIH-MSP 2010: 284-287 | |
| c31 | Wen-Ching Lin, Ming-Der Shieh, Chien-Ming Wu: Design of high-speed bit-serial divider in GF(2m). ISCAS 2010: 713-716 | |
| c30 | Hsin-Fu Luo, Ming-Der Shieh, Yi-Jun Liu, Chien-Ming Wu: Efficient memory management for FFT processors. ISCAS 2010: 3737-3740 | |
| c29 | Yung-Kuei Lu, Ming-Der Shieh, Chien-Ming Wu: Low-complexity Reed-Solomon decoder for optical communications. ISCAS 2010: 4173-4176 | |
| c28 | Shih-Hao Fang, Ju-Ya Chen, Ming-Der Shieh, Jing-Shiun Lin: Subspace-Based Blind Channel Estimation for OFDM Systems with Conjugate-Symmetric Property. VTC Spring 2010: 1-5 | |
| 2009 | ||
| j12 | Chia-Cheng Lo, Ying-Jhong Zeng, Ming-Der Shieh: Design of a High-Throughput CABAC Encoder. IEICE Transactions 92-D(4): 681-688 (2009) | |
| j11 | Ming-Der Shieh, Tai-Ping Wang, Der-Wei Yang: Low-power register-exchange survivor memory architectures for Viterbi decoders. IET Circuits, Devices & Systems 3(2): 83-90 (2009) | |
| j10 | Ming-Der Shieh, Jun-Hong Chen, Wen-Ching Lin, Chien-Ming Wu: An Efficient Multiplier/Divider Design for Elliptic Curve Cryptosystem over GF(2m). J. Inf. Sci. Eng. 25(5): 1555-1573 (2009) | |
| j9 | Ming-Der Shieh, Jun-Hong Chen, Wen-Ching Lin, Hao-Hsuan Wu: A New Algorithm for High-Speed Modular Multiplication Design. IEEE Trans. on Circuits and Systems 56-I(9): 2009-2019 (2009) | |
| c27 | Chia-Cheng Lo, Jung-Guan Luo, Ming-Der Shieh: Hardware/Software Codesign of Resource Constrained Real-Time Systems. IAS 2009: 177-180 | |
| c26 | Jun-Jie Zhu, Wen-Ching Lin, Jheng-Hao Ye, Ming-Der Shieh: Efficient Software-Based Self-Test Methods for Embedded Digital Signal Processors. Asian Test Symposium 2009: 206-211 | |
| c25 | Wen-Ching Lin, Ming-Der Shieh, Chien-Ming Wu: Flexible GF(2m) Divider Design for Cryptographic Applications. ISCAS 2009: 25-28 | |
| c24 | Shih-Hao Fang, Ju-Ya Chen, Ming-Der Shieh, Jing-Shiun Lin: A Generalized Blind Channel Estimation Algorithm for OFDM Systems with Cyclic Prefix. ISCAS 2009: 2469-2472 | |
| c23 | Shih-Hao Fang, Ju-Ya Chen, Ming-Der Shieh, Jing-Shiun Lin: Modified Subspace Based Channel Estimation Algorithm for OFDM Systems. VTC Spring 2009 | |
| 2008 | ||
| j8 | Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu: Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders. IEICE Transactions 91-D(9): 2300-2311 (2008) | |
| j7 | Chin-Long Wey, Ming-Der Shieh, Shin-Yo Lin: Algorithms of Finding the First Two Minimum Values and Their Hardware Implementation. IEEE Trans. on Circuits and Systems 55-I(11): 3430-3437 (2008) | |
| j6 | Ming-Der Shieh, Jun-Hong Chen, Hao-Hsuan Wu, Wen-Ching Lin: A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem. IEEE Trans. VLSI Syst. 16(9): 1151-1161 (2008) | |
| c22 | Jun-Hong Chen, Sue-Jing Huang, Wen-Ching Lin, Yung-Kuei Lu, Ming-Der Shieh: Exploration of Low-Cost Configurable S-Box Designs for AES Applications. ICESS 2008: 422-428 | |
| c21 | Wen-Ching Lin, Jun-Hong Chen, Ming-Der Shieh: A new look-up table-based multiplier/squarer design for cryptosystems over GF(2m). ISCAS 2008: 464-467 | |
| c20 | Jun-Hong Chen, Wen-Ching Lin, Hao-Hsuan Wu, Ming-Der Shieh: High-speed modular multiplication design for public-key cryptosystems. ISCAS 2008: 680-683 | |
| 2007 | ||
| c19 | Jun-Hong Chen, Haw-Shiuan Wu, Ming-Der Shieh, Wen-Ching Lin: A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem. ISCAS 2007: 3780-3783 | |
| 2006 | ||
| j5 | Ming-Der Shieh, Jun-Hong Chen, Chien-Ming Wu: High-Speed Design of Montgomery Inverse Algorithm over GF(2m). IEICE Transactions 89-A(2): 559-565 (2006) | |
| c18 | Jun-Hong Chen, Ming-Der Shieh, Haw-Shiuan Wu, Wen-Ching Lin: Asynchronous Design of Modular Multiplication Using Adaptive Radix Computation. APCCAS 2006: 606-609 | |
| c17 | Jing-Shiun Lin, Chung-Kung Lee, Ming-Der Shieh, Jun-Hong Chen: High-speed CRC design for 10 Gbps applications. ISCAS 2006 | |
| c16 | Ming-Der Shieh, Yung-Kuei Lu, Shen-Ming Chung, Jun-Hong Chen: Design and implementation of efficient Reed-Solomon decoders for multi-mode applications. ISCAS 2006 | |
| c15 | Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu, Chun-Ming Huang: Efficient path metric access for reducing interconnect overhead in Viterbi decoders. ISCAS 2006 | |
| 2005 | ||
| j4 | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen: VLSI architectural design tradeoffs for sliding-window log-MAP decoders. IEEE Trans. VLSI Syst. 13(4): 439-447 (2005) | |
| c14 | Jun-Hong Chen, Ming-Der Shieh, Chien-Ming Wu: Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography. ISCAS (5) 2005: 5254-5257 | |
| 2004 | ||
| j3 | Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang: High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). IEEE Trans. Computers 53(3): 375-380 (2004) | |
| c13 | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo: VLSI architecture exploration for sliding-window Log-MAP decoders. ISCAS (2) 2004: 513-516 | |
| 2003 | ||
| c12 | Chien-Ming Wu, Ming-Der Shieh, Hsin-Fu Lo, Min-Hsiung Hu: Implementation of channel demodulator for DAB system. ISCAS (2) 2003: 137-140 | |
| 2002 | ||
| c11 | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu: Memory arrangements in turbo decoders using sliding-window BCJR algorithm. ISCAS (5) 2002: 557-560 | |
| c10 | Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang: An area-efficient systolic division circuit over GF(2/sup m/) for secure communication. ISCAS (5) 2002: 733-736 | |
| 2001 | ||
| j2 | Ming-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen, Hsin-Fu Lo: A Systematic Approach for Parallel CRC Computations. J. Inf. Sci. Eng. 17(3): 445-461 (2001) | |
| c9 | Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang: Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. ISCAS (4) 2001: 33-36 | |
| c8 | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu: VLSI architecture of extended in-place path metric update for Viterbi decoders. ISCAS (4) 2001: 206-209 | |
| c7 | Ming-Hwa Sheu, Ho-En Liao, Shih Tsung Kan, Ming-Der Shieh: A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. ISCAS (4) 2001: 446-449 | |
| c6 | Hsin-Fu Lo, Ming-Der Shieh, Chien-Ming Wu: Design of an efficient FFT processor for DAB system. ISCAS (4) 2001: 654-657 | |
| 2000 | ||
| c5 | Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu: High-speed generation of LFSR signatures. Asian Test Symposium 2000: 222- | |
| 1999 | ||
| c4 | Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu: A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. ISCAS (1) 1999: 500-503 | |
| c3 | Jin-Chuan Huang, Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu: An area-efficient versatile Reed-Solomon decoder for ADSL. ISCAS (1) 1999: 517-520 | |
| 1998 | ||
| j1 | Chin-Long Wey, Ming-Der Shieh: Design of a High-Speed Square Generator. IEEE Trans. Computers 47(9): 1021-1026 (1998) | |
| 1996 | ||
| c2 | ||
| 1993 | ||
| c1 | Chin-Long Wey, Ming-Der Shieh, P. David Fisher: ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits. ICCD 1993: 159-162 | |
Colors in the list of coauthors
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