Changsik Shin

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	2011
j2		Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, Youngsoo Shin: Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. Journal of Circuits, Systems, and Computers 20(8): 1547-1569 (2011)
	2009
j1		Eunjoo Choi, Changsik Shin, Youngsoo Shin: ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 451-456 (2009)
	2008
c1		Eunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin: Power-gating-aware high-level synthesis. ISLPED 2008: 39-44

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