Youngsoo Shin

Sangmin Kim, Duckhwan Kim, Youngsoo Shin: Pulsed-latch ASIC synthesis in industrial design flow. ASP-DAC 2013: 356-361

Jun Seomun, Insup Shin, Youngsoo Shin: Synthesis of Active-Mode Power-Gating Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 31(3): 391-403 (2012)

Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin: Clock Gating Synthesis of Pulsed-Latch Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 31(7): 1019-1030 (2012)

Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin: HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. IEEE Trans. VLSI Syst. 20(4): 593-604 (2012)

Nam Sung Kim, Abhishek A. Sinkar, Jun Seomun, Youngsoo Shin: Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating. IEEE Trans. VLSI Syst. 20(10): 1885-1890 (2012)

Insup Shin, Donkyu Baek, Youngsoo Shin: Introducing irregularity to routing architecture of structured ASIC for better routability. FPT 2012: 224-228

Youngsoo Shin, Seungwhun Paik: Pulsed-Latch Circuits: A New Dimension in ASIC Design. IEEE Design & Test of Computers 28(6): 50-57 (2011)

Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, Youngsoo Shin: Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. Journal of Circuits, Systems, and Computers 20(8): 1547-1569 (2011)

Seungwhun Paik, Seonggwan Lee, Youngsoo Shin: Retiming Pulsed-Latch Circuits With Regulating Pulse Width. IEEE Trans. on CAD of Integrated Circuits and Systems 30(8): 1114-1127 (2011)

Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang: Pulsed-Latch Aware Placement for Timing-Integrity Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 30(12): 1856-1869 (2011)

Jun Seomun, Youngsoo Shin: Design and Optimization of Power-Gated Circuits With Autonomous Data Retention. IEEE Trans. VLSI Syst. 19(2): 227-236 (2011)

Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin: Pulser gating: A clock gating of pulsed-latch circuits. ASP-DAC 2011: 190-195

Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin: Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. ASP-DAC 2011: 376-381

Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin: Thermal signature: a simple yet accurate thermal index for floorplan optimization. DAC 2011: 108-113

Seungwhun Paik, Gi-Joon Nam, Youngsoo Shin: Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power. ICCAD 2011: 640-646

Byunghee Choi, Youngsoo Shin: Lookup Table-Based Adaptive Body biasing of Multiple Macros for Process Variation Compensation and Low Leakage. Journal of Circuits, Systems, and Computers 19(7): 1449-1464 (2010)

Hyein Lee, Seungwhun Paik, Youngsoo Shin: Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 355-366 (2010)

Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin: HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 657-670 (2010)

Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, Takayasu Sakurai: Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs. ACM Trans. Design Autom. Electr. Syst. 15(4) (2010)

Hyung-Ock Kim, Bong Hyun Lee, Jong-Tae Kim, Jung Yun Choi, Kyu-Myung Choi, Youngsoo Shin: Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS. IEEE Trans. VLSI Syst. 18(3): 505-509 (2010)

Jun Seomun, Seungwhun Paik, Youngsoo Shin: Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design. ASP-DAC 2010: 581-586

Seungwhun Paik, Lee-eun Yu, Youngsoo Shin: Statistical time borrowing for pulsed-latch circuit designs. ASP-DAC 2010: 675-680

Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang: Pulsed-latch aware placement for timing-integrity optimization. DAC 2010: 280-285

Jun Seomun, Insup Shin, Youngsoo Shin: Synthesis and implementation of active mode power gating circuits. DAC 2010: 487-492

Seungwhun Paik, Sangmin Kim, Youngsoo Shin: Wakeup synthesis and its buffered tree construction for power gating circuit designs. ISLPED 2010: 413-418

Youngsoo Shin, Seungwhun Paik, Hyung-Ock Kim: Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 327-339 (2009)

Eunjoo Choi, Changsik Shin, Youngsoo Shin: ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 451-456 (2009)

Jaehyun Kim, Chungki Oh, Youngsoo Shin: Minimizing leakage power of sequential circuits through mixed-V_t flip-flops and multi-V_t combinational gates. ACM Trans. Design Autom. Electr. Syst. 15(1) (2009)

Insup Shin, Seungwhun Paik, Youngsoo Shin: Register allocation for high-level synthesis using dual supply voltages. DAC 2009: 937-942

Seungwhun Paik, Insup Shin, Youngsoo Shin: HLS-l: High-level synthesis of high performance latch-based circuits. DATE 2009: 1112-1117

Seonggwan Lee, Seungwhun Paik, Youngsoo Shin: Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits. ICCAD 2009: 375-380

Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin: Frequency and yield optimization using power gates in power-constrained designs. ISLPED 2009: 121-126

Jun Seomun, Jae-Hyun Kim, Youngsoo Shin: Skewed Flip-Flop and Mixed-V_t Gates for Minimizing Leakage in Sequential Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 1956-1968 (2008)

Jinseob Jeong, Seungwhun Paik, Youngsoo Shin: Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation. ASP-DAC 2008: 629-634

Seungwhun Paik, Youngsoo Shin: Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. DAC 2008: 600-605

Hyein Lee, Seungwhun Paik, Youngsoo Shin: Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. ICCAD 2008: 224-229

Eunjoo Choi, Youngsoo Shin: 3-D thermal simulation with dynamic power profiles. ISCAS 2008: 2765-2768

Eunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin: Power-gating-aware high-level synthesis. ISLPED 2008: 39-44

Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi: Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. IEEE Trans. VLSI Syst. 15(7): 758-766 (2007)

Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. ASP-DAC 2007: 654-659

Jun Seomun, Jaehyun Kim, Youngsoo Shin: Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits. DAC 2007: 103-106

Jaehyun Kim, Youngsoo Shin: Minimizing leakage power in sequential circuits by using mixed V_t flip-flops. ICCAD 2007: 797-802

Youngsoo Shin, Hyung-Ock Kim: Cell-Based Semicustom Design of Zigzag Power Gating Circuits. ISQED 2007: 527-532

Byunghee Choi, Youngsoo Shin: Lookup Table-Based Adaptive Body Biasing of Multiple Macros. ISQED 2007: 533-538

Youngsoo Shin, Junghyup Lee: Power Analysis of VLSI Interconnect with RLC Tree Models and Model Reduction. Journal of Circuits, Systems, and Computers 15(3): 399-408 (2006)

Hyung-Ock Kim, Youngsoo Shin: Analysis and optimization of gate leakage current of power gating circuits. ASP-DAC 2006: 565-569

Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo: Physical design methodology of power gating circuits for standard-cell-based design. DAC 2006: 109-112

Hiroshi Kawaguchi, Youngsoo Shin, Takayasu Sakurai: /spl mu/ITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications. IEEE Transactions on Multimedia 7(1): 67-74 (2005)

Hyung-Ock Kim, Youngsoo Shin: Power-aware slack distribution for hierarchical VLSI design. ISCAS (4) 2005: 4150-4153

Youngsoo Shin, Hyung-Ock Kim: Analysis of power consumption in VLSI global interconnects. ISCAS (5) 2005: 4713-4716

Subhrajit Bhattacharya, John A. Darringer, Daniel L. Ostapko, Youngsoo Shin: A Mask Reuse Methodology for Reducing System-on-a-Chip Cost. ISQED 2005: 482-487

Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu: Architecting voltage islands in core-based system-on-a-chip designs. ISLPED 2004: 180-185

Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal: SEAS: a system for early analysis of SoCs. CODES+ISSS 2003: 150-155

John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin: Early analysis tools for system-on-a-chip design. IBM Journal of Research and Development 46(6): 691-708 (2002)

Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi: Partial bus-invert coding for power optimization of application-specific systems. IEEE Trans. VLSI Syst. 9(2): 377-383 (2001)

Youngsoo Shin, Kiyoung Choi, Young-Hoon Chang: Narrow bus encoding for low-power DSP systems. IEEE Trans. VLSI Syst. 9(5): 656-660 (2001)

Youngsoo Shin, Takayasu Sakurai: Coupling-Driven Bus Design for Low-Power Application-Specific Systems. DAC 2001: 750-753

Youngsoo Shin, Takayasu Sakurai: Estimation of power distribution in VLSI interconnects. ISLPED 2001: 370-375

Youngsoo Shin, Kiyoung Choi: Narrow bus encoding for low power systems. ASP-DAC 2000: 217-220

Youngsoo Shin, Daehong Kim, Kiyoung Choi: Schedulability-driven performance analysis of multiple mode embedded real-time systems. DAC 2000: 495-500

Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai: Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. ICCAD 2000: 365-368

Youngsoo Shin, Kiyoung Choi: Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems. DAC 1999: 134-139

Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Kiyoung Choi: An Integrated Cosimulation Environment for Heterogeneous Systems Prototyping. Design Autom. for Emb. Sys. 3(2-3): 163-186 (1998)

Youngsoo Shin, Kiyoung Choi: Rate Assignment for Embedded Reactive Real-Time Systems. EUROMICRO 1998: 10237-

Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi: Partial bus-invert coding for power optimization of system level bus. ISLPED 1998: 127-129

Youngsoo Shin, Kiyoung Choi: Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign. CODES 1997: 3-8

Youngsoo Shin, Kiyoung Choi: Software synthesis through task decomposition by dependency analysis. ICCAD 1996: 98-104

Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi Ha: An integrated hardware-software cosimulation environment for heterogeneous systems prototyping. ASP-DAC 1995

Yongjoo Kim, Youngsoo Shin, Kyuseok Kim, Jae-Hee Won, Kiyoung Choi: Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification. ISCAS 1995: 924-927