Thomas R. Shiple

Michael Mendler, Thomas R. Shiple, Gérard Berry: Constructive Boolean circuits and the exactness of timed ternary simulation. Formal Methods in System Design 40(3): 283-329 (2012)

Stephen M. Plaza, Prashant Saxena, Thomas R. Shiple, Pei-Hsin Ho: Multi-mode redundancy removal. ISQED 2011: 791-799

Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Formula-Dependent Equivalence for Compositional CTL Model Checking. Formal Methods in System Design 21(2): 193-224 (2002)

In-Ho Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl Pixley: Simplifying Circuits for Formal Verification Using Parametric Representation. FMCAD 2002: 52-69

Hee-Hwan Kwak, In-Ho Moon, James H. Kukula, Thomas R. Shiple: Combinational equivalence checking through function transformation. ICCAD 2002: 526-533

Adnan Aziz, James H. Kukula, Thomas R. Shiple, Jun Yuan: Efficient control state-space search. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 332-336 (2001)

Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, James H. Kukula, Thomas R. Shiple, Helmut Veith, Dong Wang: Non-linear Quantification Scheduling in Image Computation. ICCAD 2001: 293-

James H. Kukula, Thomas R. Shiple: Building Circuits from Relations. CAV 2000: 113-123

Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James H. Kukula, Robert F. Damiano, Valeria Bertacco, Jerry Taylor, Jiang Long: Smart Simulation Using Collaborative Formal and Simulation Engines. ICCAD 2000: 120-126

In-Ho Moon, James H. Kukula, Thomas R. Shiple, Fabio Somenzi: Least fixpoint approximations for reachability analysis. ICCAD 1999: 41-44

Thomas R. Shiple, James H. Kukula, Rajeev K. Ranjan: A Comparison of Presburger Engines for EFSM Reachability. CAV 1998: 280-292

Kavita Ravi, Kenneth L. McMillan, Thomas R. Shiple, Fabio Somenzi: Approximation and Decomposition of Binary Decision Diagrams. DAC 1998: 445-450

Adnan Aziz, James H. Kukula, Thomas R. Shiple: Hybrid Verification Using Saturated Simulation. DAC 1998: 615-618

James H. Kukula, Thomas R. Shiple, Adnan Aziz: Techniques for Implicit State Enumeration of EFSMs. FMCAD 1998: 469-482

Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa: VIS: A System for Verification and Synthesis. CAV 1996: 428-432

Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa: VIS. FMCAD 1996: 248-256

Adnan Aziz, Thomas R. Shiple, Vigyan Singhal: Formula-Dependent Equivalence for Compositional CTL Model Checking. CAV 1994: 324-337

Thomas R. Shiple, Ramin Hojati, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton: Heuristic Minimization of BDDs Using Don't Cares. DAC 1994: 225-231

Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: HSIS: A BDD-Based Environment for Formal Verification. DAC 1994: 454-459

Kevin Covey, Sandra Murdock, Thomas R. Shiple: Two-phase Logic Design by Hardware Flowcharts. ICCD 1994: 368-380

Ramin Hojati, Thomas R. Shiple, Robert K. Brayton, Robert P. Kurshan: A Unified Approach to Language Containment and Fair CTL Model Checking. DAC 1993: 475-481

Thomas R. Shiple, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton: Automatic Reduction in CTL Compositional Model Checking. CAV 1992: 234-247

Massimiliano Chiodo, Thomas R. Shiple, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton: Automatic compositional minimization in CTL model checking. ICCAD 1992: 172-178