Miguel Lino Silva

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	2012
j4		Miguel Lino Silva, João Canas Ferreira: Run-time generation of partial FPGA configurations. Journal of Systems Architecture - Embedded Systems Design 58(1): 24-37 (2012)
j3		Miguel Lino Silva, João Canas Ferreira: Run-time generation of partial FPGA configurations for subword operations. Microprocessors and Microsystems - Embedded Hardware Design 36(5): 365-374 (2012)
	2010
c3		Miguel Lino Silva, João Canas Ferreira: Creation of Partial FPGA Configurations at Run-Time. DSD 2010: 80-87
	2008
c2		Miguel Lino Silva, João Canas Ferreira: Generation of partial FPGA configurations at run-time. FPL 2008: 367-372
	2007
j2		Miguel Lino Silva, João Canas Ferreira: Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems. IET Computers & Digital Techniques 1(5): 461-471 (2007)
	2006
j1		Miguel Lino Silva, João Canas Ferreira: Support for partial run-time reconfiguration of platform FPGAs. Journal of Systems Architecture 52(12): 709-726 (2006)
	2005
c1		Miguel Lino Silva, João Canas Ferreira: Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs. DSD 2005: 383-387

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