Virendra Singh

Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal: Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. VLSI Design 2013

Suraj Sindia, Vishwani D. Agrawal, Virendra Singh: Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing. J. Electronic Testing 28(4): 541-549 (2012)

Suraj Sindia, Vishwani D. Agrawal, Virendra Singh: Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients. J. Electronic Testing 28(5): 757-771 (2012)

Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita: SEU tolerant robust memory cell design. IOLTS 2012: 13-18

Suraj Sindia, Fa Foster Dai, Vishwani D. Agrawal, Virendra Singh: Impact of process variations on computers used for image processing. ISCAS 2012: 1444-1447

Pawan Kumar, Virendra Singh: Efficient regular expression pattern matching for network intrusion detection systems using modified word-based automata. SIN 2012: 103-110

Jaynarayan T. Tudu, Deepak Malani, Virendra Singh: ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits. VDAT 2012: 172-179

Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita: SEU Tolerant Robust Latch Design. VDAT 2012: 223-232

V. Prasanth, Virendra Singh, Rubin A. Parekhji: Derating based hardware optimizations in soft error tolerant designs. VTS 2012: 282-287

Manoj Singh Gaur, Atilla Elçi, Oleg B. Makarevich, Mehmet A. Orgun, Virendra Singh (Eds.): 5th International Conference of Security of Information and Networks, SIN '12, Jaipur, India, October 22 - 26, 2012. ACM 2012, isbn 978-1-4503-1668-2

Mohammed Abdul Razzaq, Virendra Singh, Adit D. Singh: SSTKR: Secure and Testable Scan Design through Test Key Randomization. Asian Test Symposium 2011: 60-65

Suraj Sindia, Vishwani D. Agrawal, Virendra Singh: Test and Diagnosis of Analog Circuits Using Moment Generating Functions. Asian Test Symposium 2011: 371-376

Anzhela Matrosova, Alexey Melnikov, Ruslan Mukhamedov, Virendra Singh: Selection of the state variables for partial enhanced scan techniques. EWDTS 2011: 285-290

Harsh Gidra, Israrul Haque, Nitin P. Kumar, M. Sargurunathan, M. S. Gaur, Vijay Laxmi, Mark Zwolinski, Virendra Singh: Parallelizing TUNAMI-N1 Using GPGPU. HPCC 2011: 845-850

Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson: Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. ICCD 2011: 419-426

V. Prasanth, Virendra Singh, Rubin A. Parekhji: Reduced overhead soft error mitigation using error control coding techniques. IOLTS 2011: 163-168

Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita: SEU tolerant SRAM cell. ISQED 2011: 597-602

Virendra Singh, Masahiro Fujita: Tutorial: "Post silicon debug of SOC designs". SoCC 2011: 18

Manas Kumar Puthal, Virendra Singh, M. S. Gaur, Vijay Laxmi: C-Routing: An adaptive hierarchical NoC routing methodology. VLSI-SoC 2011: 392-397

Suraj Sindia, Vishwani D. Agrawal, Virendra Singh: Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. VTS 2011: 64-69

Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, Adit D. Singh: Modified Scan Flip-Flop for Low Power Testing. Asian Test Symposium 2010: 367-370

Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson: Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. DATE 2010: 1572-1577

Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson: Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing. DELTA 2010: 281-285

Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson: Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding. DSN 2010: 121-130

Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh: Modified T-Flip-Flop based scan cell for RAS. European Test Symposium 2010: 113-118

Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara: Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. European Test Symposium 2010: 259

Anjela Matrosova, V. Lipsky, Alexey Melnikov, Virendra Singh: Path delay faults and ENF. EWDTS 2010: 164-167

Aditi Kajala, Gayaprasad Sinsinwar, Rahul Raj Choudhary, Jaynarayan T. Tudu, Virendra Singh: On selection of state variables for delay test of identical functional units. EWDTS 2010: 200-203

Viney Kumar, Rahul Raj Choudhary, Virendra Singh: FREP: A soft error resilient pipelined RISC architecture. EWDTS 2010: 330-333

N. S. Vinay, Indira Rawaty, Erik Larsson, M. S. Gaur, Virendra Singh: Thermal aware test scheduling for stacked multi-chip-modules. EWDTS 2010: 343-349

K. R. Vinutha, Virendra Singh, Anzhela Matrosova, M. S. Gaur: Fault grading using Instruction-Execution graph. EWDTS 2010: 350-357

Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita: SEU tolerant SRAM for FPGA applications. FPT 2010: 491-494

Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara: Graph theoretic approach for scan cell reordering to minimize peak shift power. ACM Great Lakes Symposium on VLSI 2010: 73-78

Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson: Energy-efficient redundant execution for chip multiprocessors. ACM Great Lakes Symposium on VLSI 2010: 143-146

V. Prasanth, Virendra Singh, Rubin A. Parekhji: Robust detection of soft errors using delayed capture methodology. IOLTS 2010: 277-282

A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh: Test application time minimization for RAS using basis optimization of column decoder. ISCAS 2010: 2614-2617

Naveen Choudhary, Manoj Singh Gaur, Vijay Laxmi, Virendra Singh: Genetic algorithm based topology generation for application specific Network-on-Chip. ISCAS 2010: 3156-3159

Suraj Sindia, Virendra Singh, Vishwani D. Agrawal: Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. VLSI Design 2010: 288-293

Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh: On Minimization of Test Application Time for RAS. VLSI Design 2010: 393-398

Suraj Sindia, Virendra Singh, Vishwani D. Agrawal: Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. Asian Test Symposium 2009: 63-68

K. G. Deepak, Robinson Reyna, Virendra Singh, Adit D. Singh: Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. Asian Test Symposium 2009: 237-240

Mikael Väyrynen, Virendra Singh, Erik Larsson: Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips. DATE 2009: 484-489

Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal: On Minimization of Peak Power for Scan Circuit during Test. European Test Symposium 2009: 25-30

Suraj Sindia, Virendra Singh, Vishwani D. Agrawal: Polynomial coefficient based DC testing of non-linear analog circuits. ACM Great Lakes Symposium on VLSI 2009: 69-74

Reshma C. Jumani, Niraj Bharatkumar Jain, Virendra Singh, Kewal K. Saluja: DX-compactor: distributed X-compaction for SoCs. ACM Great Lakes Symposium on VLSI 2009: 505-510

Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. IEEE Trans. VLSI Syst. 14(11): 1203-1215 (2006)

Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Delay Fault Testing of Processor Cores in Functional Mode. IEICE Transactions 88-D(3): 610-618 (2005)

Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Testing Superscalar Processors in Functional Mode. FPL 2005: 747-750

Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-based delay fault self-testing of pipelined processor cores. ISCAS (6) 2005: 5686-5689

Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-Based Delay Fault Self-Testing of Processor Cores. VLSI Design 2004: 933-

Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Software-Based Delay Fault Testing of Processor Cores. Asian Test Symposium 2003: 68-71