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 | 1998 | |
|---|---|---|
| j3 |      | Zohair Sahraoui, Francky Catthoor, Paul Six, Hugo De Man: Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation. J. Electronic Testing 12(3): 217-238 (1998) |
| c9 | | Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Miguel Miranda, Kris Croes, Sven Wuytack, Gjalt G. de Jong, Francky Catthoor, Diederik Verkest, Paul Six, Hugo De Man: Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer. DAC 1998: 76-81 |
| 1995 | ||
| c8 | | Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De Man: Timing optimization by bit-level arithmetic transformations. EURO-DAC 1995: 48-53 |
| c7 | | Zohair Sahraoui, Paul Six, Ivo Bolsens, Hugo De Man: Search space reduction through clustering in test generation. EURO-DAC 1995: 242-247 |
| 1992 | ||
| c6 |  | Augusli Kifli, R. De Wulf, J. Zegers, Gert Goossens, Paul Six, Hugo De Man: Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers. Synthesis for Control Dominated Circuits 1992: 61-71 |
| c5 | | Evagelos Katsadas, Zohair Sahraoui, M. Wouters, Veerle Derudder, Ivo Bolsens, Paul Six, Hugo De Man: Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building Blocks. Synthesis for Control Dominated Circuits 1992: 167-181 |
| 1991 | ||
| j2 | | Paul Vanoostende, Paul Six, Hugo De Man: DARSI: RC data reduction [VLSI simulation]. IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 493-500 (1991) |
| 1990 | ||
| c4 | | H. Cai, Stefaan Note, Paul Six, Hugo De Man: A Data Path Layout Assembler for High Performance DSP Circuits. DAC 1990: 306-311 |
| c3 | | J. Zegers, Paul Six, Jan M. Rabaey, Hugo De Man: CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler. EURO-DAC 1990: 617-621 |
| 1989 | ||
| j1 | | I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man: REDUSA: module generation by automatic elimination of superfluous blocks in regular structures. IEEE Trans. on CAD of Integrated Circuits and Systems 8(9): 989-998 (1989) |
| c2 | | I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man: REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures. DAC 1989: 694-697 |
| 1986 | ||
| c1 | | Paul Six, Luc J. M. Claesen, Jan M. Rabaey, Hugo De Man: An intelligent module generator environment. DAC 1986: 730-735 |
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