| 2007 | ||
|---|---|---|
| c3 | Ales Smrcka, Tomás Vojnar: Verifying Parametrised Hardware Designs Via Counter Automata. Haifa Verification Conference 2007: 51-68 | |
| 2006 | ||
| c2 | Ales Smrcka, Vojtech Rehák, Tomás Vojnar, David Safránek, Petr Matousek, Z. Rehák: Verifying VHDL Designs with Multiple Clocks in SMV. FMICS/PDMC 2006: 148-164 | |
| 2005 | ||
| c1 | Petr Matousek, Ales Smrcka, Tomás Vojnar: High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design. CHARME 2005: 371-375 | |
| 1 | Petr Matousek | |
| 2 | Vojtech Rehák | |
| 3 | Z. Rehák | |
| 4 | David Safránek | |
| 5 | Tomás Vojnar |
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