Ki-Whan Song

Yong-Sung Cho, Il-Han Park, Sangyong Yoon, Nam-Hee Lee, Sang-Hyun Joo, Ki-Whan Song, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Young-Hyun Jun: Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH. J. Solid-State Circuits 48(4): 948-959 (2013)

Daeyeal Lee, Ik Joon Chang, Sangyong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, ByungJun Min, Sung-Won Yun, Ji-Sang Lee, Il-Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang-Hyun Joo, Jin-Young Chun, Jung-No Im, Seunghyuk Kwon, Seokjun Ham, Ansoo Park, Jae-Duk Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, Hoosung Kim, Ki-Whan Song, Byung-Gil Jeon, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Youngho Lim, Young-Hyun Jun: A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. ISSCC 2012: 430-432

Myounggon Kang, Ki-Whan Song, Byung-Gook Park, Hyungcheol Shin: The novel SCR-based ESD protection with low triggering and high holding voltages. Microelectronics Journal 42(6): 837-839 (2011)

Hoeju Chung, Byung-Hoon Jeong, ByungJun Min, Youngdon Choi, Beak-Hyung Cho, Junho Shin, Jinyoung Kim, Jung Sunwoo, Joon-min Park, Qi Wang, Yong-jun Lee, Sooho Cha, Dukmin Kwon, Sangtae Kim, Sunghoon Kim, Yoohwan Rho, Mu-Hui Park, Jaewhan Kim, Ickhyun Song, Sunghyun Jun, Jaewook Lee, KiSeung Kim, Ki-won Lim, Won-ryul Chung, ChangHan Choi, HoGeun Cho, Inchul Shin, Woochul Jun, Seokwon Hwang, Ki-Whan Song, KwangJin Lee, Sang-whan Chang, Woo-Yeong Cho, Jei-Hwan Yoo, Young-Hyun Jun: A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW. ISSCC 2011: 500-502

Ki-Whan Song, Jinyoung Kim, Jae-Man Yoon, Sua Kim, Huijung Kim, Hyun-Woo Chung, Hyungi Kim, Kanguk Kim, Hwan-Wook Park, Hyun Chul Kang, Nam-Kyun Tak, Dukha Park, Woo-Seop Kim, Yeong-Taek Lee, Yong Chul Oh, Gyo-Young Jin, Jei-Hwan Yoo, Donggun Park, Kyungseok Oh, Changhyun Kim, Young-Hyun Jun: A 31 ns Random Cycle VCAT-Based 4F ² DRAM With Manufacturability and Enhanced Cell Efficiency. J. Solid-State Circuits 45(4): 880-888 (2010)

Ki-Whan Song, Sang-Hoon Lee, Dae Hwan Kim, Kyung Rok Kim, Jaewoo Kyung, Gwanghyeon Baek, Chun-An Lee, Jong Duk Lee, Byung-Gook Park: Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic. ISMVL 2003: 267-272