Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Sudarshan K. Srinivasan
2010 – today
- 2012
[j10]Sudarshan K. Srinivasan, Y. Cai, Koushik Sarker: Refinement-based verification of elastic pipelined systems. IET Computers & Digital Techniques 6(2): 136-152 (2012)- 2011
- [j9]Raj S. Katti, Sudarshan K. Srinivasan, Aida Vosoughi: On the Security of Randomized Arithmetic Codes Against Ciphertext-Only Attacks. IEEE Transactions on Information Forensics and Security 6(1): 19-27 (2011)
- [c14]Sudarshan K. Srinivasan, Raj S. Katti: Desynchronization: design for verification. FMCAD 2011: 215-222
- 2010
- [j8]Sudarshan K. Srinivasan: Optimization Techniques for Verification of Out-of-Order Execution Machines. J. Electrical and Computer Engineering 2010 (2010)
- [j7]Sudarshan K. Srinivasan: Automatic Refinement Checking of Pipelines with Out-of-Order Execution. IEEE Trans. Computers 59(8): 1138-1144 (2010)
- [c13]Rajesh Kavasseri, Sudarshan K. Srinivasan: Joint optimal placement of PMU and conventional measurements in power systems. ISCAS 2010: 3449-3452
2000 – 2009
- 2009
- [j6]Sudarshan K. Srinivasan, Koushik Sarker, Rajendra S. Katti: Verification of Synchronous Elastic Processors. Embedded Systems Letters 1(1): 14-18 (2009)
- [j5]Sudarshan K. Srinivasan, Koushik Sarker, Rajendra S. Katti: Token-Aware Completion Functions for Elastic Processor Verification. J. Electrical and Computer Engineering 2009 (2009)
- [c12]Raj S. Katti, Sudarshan K. Srinivasan: Efficient Hardware Implementation of a New Pseudo-random Bit Sequence Generator. ISCAS 2009: 1393-1396
- [c11]Sudarshan K. Srinivasan, Raj S. Katti: Verification of Desynchronized Circuits. ISCAS 2009: 1509-1512
- 2008
- [j4]Panagiotis Manolios, Sudarshan K. Srinivasan: Automatic verification of safety and liveness for pipelined machines using WEB refinement. ACM Trans. Design Autom. Electr. Syst. 13(3) (2008)
- [j3]Panagiotis Manolios, Sudarshan K. Srinivasan: A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification. IEEE Trans. VLSI Syst. 16(4): 353-364 (2008)
- 2007
- [c10]Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon: BAT: The Bit-Level Analysis Tool. CAV 2007: 303-306
- 2006
- [j2]Panagiotis Manolios, Sudarshan K. Srinivasan: A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures. J. Autom. Reasoning 37(1-2): 93-116 (2006)
- [c9]Roma Kane, Panagiotis Manolios, Sudarshan K. Srinivasan: Monolithic verification of deep pipelines with collapsed flushing. DATE 2006: 1234-1239
- [c8]Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon: Automatic memory reductions for RTL model verification. ICCAD 2006: 786-793
- 2005
- [c7]Panagiotis Manolios, Sudarshan K. Srinivasan: A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems. CHARME 2005: 363-366
- [c6]Panagiotis Manolios, Sudarshan K. Srinivasan: Refinement Maps for Efficient Verification of Processor Models. DATE 2005: 1304-1309
- [c5]Panagiotis Manolios, Sudarshan K. Srinivasan: Verification of executable pipelined machines with bit-level interfaces. ICCAD 2005: 855-862
- [c4]Panagiotis Manolios, Sudarshan K. Srinivasan: A complete compositional reasoning framework for the efficient verification of pipelined machines. ICCAD 2005: 863-870
- [c3]Panagiotis Manolios, Sudarshan K. Srinivasan: A computationally ef~cient method based on commitment re~nement maps for verifying pipelined machines. MEMOCODE 2005: 188-197
- 2004
- [c2]Panagiotis Manolios, Sudarshan K. Srinivasan: Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements. DATE 2004: 168-175
- 2003
- [j1]Jun-Cheol Park, Vincent John Mooney III, Sudarshan K. Srinivasan: Combining data remapping and voltage/frequency scaling of second level memory for energy reduction in embedded systems. Microelectronics Journal 34(11): 1019-1024 (2003)
- [c1]Sudarshan K. Srinivasan, Miroslav N. Velev: Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions. MEMOCODE 2003: 65-74
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2012-12-02 20:34 CET by the dblp team