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Navin Srivastava
2010 – today
- 2012
[j4]Chuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee: Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates. IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1698-1710 (2012)- 2010
- [j3]Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee: Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060]. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 849 (2010)
- [c9]Navin Srivastava, Roberto Suaya, Kaustav Banerjee: Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. DATE 2010: 459-464
2000 – 2009
- 2009
- [j2]Navin Srivastava, Roberto Suaya, Kaustav Banerjee: Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate. IEEE Trans. on CAD of Integrated Circuits and Systems 28(7): 1047-1060 (2009)
- 2008
- [c8]Navin Srivastava, Roberto Suaya, Kaustav Banerjee: High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. DATE 2008: 426-431
- 2007
- [j1]Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood: 3D Integration for Introspection. IEEE Micro 27(1): 77-83 (2007)
- 2006
- [c7]Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava: Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. ASP-DAC 2006: 223-230
- [c6]Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood: Introspective 3D chips. ASPLOS 2006: 264-273
- [c5]Kaustav Banerjee, Navin Srivastava: Are carbon nanotubes the future of VLSI interconnections? DAC 2006: 809-814
- [c4]Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee: A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. DAC 2006: 991-996
- 2005
- [c3]Navin Srivastava, Kaustav Banerjee: Performance analysis of carbon nanotube interconnects for VLSI applications. ICCAD 2005: 383-390
- [c2]Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee: A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. ICCD 2005: 411-416
- [c1]Navin Srivastava, Xiaoning Qi, Kaustav Banerjee: Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits. ISQED 2005: 346-351
Coauthor Index
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last updated on 2012-12-02 22:01 CET by the dblp team