Walter Stechele

Jan Hartmann, Walter Stechele, Erik Maehle: Self-adaptation for Mobile Robot Algorithms Using Organic Computing Principles. ARCS 2013: 232-243

Dirk Koch, Jim Torresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele: Partial Reconfiguration on FPGAs in Practice - Tools and Applications. ARCS Workshops 2012: 297-319

Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Rüdiger Dillmann: Invasive Computing for robotic vision. ASP-DAC 2012: 207-212

Sebastian Drössler, Michael Eichhorn, S. Holzknecht, Bernd Müller-Rathgeber, Holm Rauchfuss, Michael Zwick, Erwin M. Biebl, Klaus Diepold, Jörg Eberspächer, Andreas Herkersdorf, Walter Stechele, Eckehard G. Steinbach, R. Freymann, Karl-Ernst Steinberg, Hans-Ulrich Michel: A Real-Time Capable Virtualized Information and Communication Technology Infrastructure for Automotive Systems. Advances in Real-Time Systems 2012: 275-306

Michael Feilen, Andreas Iliopoulos, Matthias Ihmig, Walter Stechele: Partitioning and context switching for a reconfigurable FPGA-based DAB receiver. DASIP 2012: 1-8

Lothar Stolz, Matthias Ihmig, Walter Stechele: An evaluation on using GPU coprocessing for software radios on a low-cost platform. DASIP 2012: 1-8

Abdelmajid Bouajila, Abdallah Lakhtel, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf: A low-overhead monitoring ring interconnect for MPSoC parameter optimization. DDECS 2012: 46-49

Michael Feilen, Matthias Ihmig, Christian Schwarzbauer, Walter Stechele: Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources. FPL 2012: 75-82

David May, Walter Stechele: An FPGA-based probability-aware fault simulator. ICSAMOS 2012: 302-309

Seunghan Han, Walter Stechele: Default Reasoning for Forensic Visual Surveillance based on Subjective Logic and Its Comparison with L-Fuzzy Set Based Approaches. IJMDEM 2(1): 38-86 (2011)

Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Andreas Herkersdorf: Autonomic System on Chip Platform. Organic Computing 2011: 413-425

Johannes Zeppenfeld, Abdelmajid Bouajila, Walter Stechele, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Andreas Herkersdorf: Applying ASoC to Multi-core Applications for Workload Management. Organic Computing 2011: 461-472

Walter Stechele, Jan Hartmann, Erik Maehle: An approach to self-learning multicore reconfiguration management applied on Robotic Vision. DASIP 2011: 217-222

Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf: An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. DDECS 2011: 225-230

Seunghan Han, Andreas Hutter, Walter Stechele: A reasoning approach to enable abductive semantic explanation upon collected observations for forensic visual surveillance. ICME 2011: 1-7

Christopher Claus, Walter Stechele: AutoVision - Reconfigurable Hardware Acceleration for Video-Based Driver Assistance. Dynamically Reconfigurable Systems 2010: 375-394

Christopher Claus, Rehan Ahmed, Florian Altenried, Walter Stechele: Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems. ARC 2010: 55-67

Seunghan Han, Bonjung Koo, Andreas Hutter, Vinay Shet, Walter Stechele: Subjective Logic Based Hybrid Approach to Conditional Evidence Fusion for Forensic Visual Surveillance. AVSS 2010: 337-344

Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich: A rapid prototyping system for error-resilient multi-processor systems-on-chip. DATE 2010: 375-380

Robert Hartl, Andreas J. Rohatschek, Walter Stechele, Andreas Herkersdorf: Architectural Vulnerability Factor Estimation with Backwards Analysis. DSD 2010: 605-612

Seunghan Han, Bonjung Koo, Walter Stechele: Subjective Logic Based Approach to Modeling Default Reasoning for Visual Surveillance. ICSC 2010: 112-119

Benjamin Kormann, Antje Neve, Gudrun Klinker, Walter Stechele: Stereo Vision based Vehicle Detection. VISAPP (2) 2010: 431-438

Seunghan Han, Bonjung Koo, Andreas Hutter, Walter Stechele: Forensic reasoning upon pre-obtained surveillance metadata using uncertain spatio-temporal rules and subjective logic. WIAMIS 2010: 1-4

Paul Zuber, Othman Bahlous, Thomas Ilnseher, Michael Ritter, Walter Stechele: Wire Topology Optimization for Low Power CMOS. IEEE Trans. VLSI Syst. 17(1): 1-11 (2009)

Christopher Claus, Robert Huitl, Joachim Rausch, Walter Stechele: Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation. FPL 2009: 138-145

Andreas Laika, Adrian Taruttis, Walter Stechele: Segmentation Through Edge-linking - Segmentation for Video-based Driver Assistance Systems. IMAGAPP 2009: 43-49

Seunghan Han, Andreas Hutter, Walter Stechele: Toward contextual forensic retrieval for visual surveillance: Challenges and an architectural approach. WIAMIS 2009: 201-204

Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele: Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. ARC 2008: 148-158

Nicolas Alt, Christopher Claus, Walter Stechele: Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments. DATE 2008: 176-181

Jürgen Becker, Michael Hübner, Robert Esser, Andreas Herkersdorf, Walter Stechele, Vera Lauer: Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. DATE 2008

Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker: Fine grain reconfigurable architectures. FPL 2008: 348

Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker: A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. FPL 2008: 535-538

Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich: A comparison of embedded reconfigurable video-processing architectures. FPL 2008: 587-590

Andreas Herkersdorf, Walter Stechele, Christian Müller-Schloer, Hartmut Schmeck: Workshop "Adaptive and Organic Systems". GI Jahrestagung (2) 2008: 731-732

Johannes Zeppenfeld, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf: Learning Classifier Tables for Autonomic Systems on Chip. GI Jahrestagung (2) 2008: 771-778

Colin Estermann, Walter Stechele, Robert Kutka, Andreas Hutter: Luminance Correction in Stereo Correspondence Based Structure from Motion. WIAMIS 2008: 179-182

Christopher Claus, Walter Stechele, Andreas Herkersdorf: Autovision - A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems (Autovision - Eine zur Laufzeit rekonfigurierbare MPSoC Architektur für zukünftige Fahrerassistenzsysteme). it - Information Technology 49(3): 181- (2007)

Christopher Claus, Johannes Zeppenfeld, Florian Helmut Müller, Walter Stechele: Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. DATE 2007: 498-503

Christopher Claus, Florian Helmut Müller, Johannes Zeppenfeld, Walter Stechele: A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration. IPDPS 2007: 1-7

Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele: Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. ISVLSI 2007: 41-46

Andreas Laika, Walter Stechele: A review of different object recognition methods for the application in driver assistance systems. WIAMIS 2007: 10

Walter Stechele, L. Alvado Cárcel, Stephan Herrmann, J. Lidón Simón: A Coprocessor for Accelerating Visual Information Processing. CoRR abs/0710.4823 (2007)

Christopher Claus, Florian Helmut Müller, Walter Stechele: Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro. ARCS Workshops 2006: 122-131

Walter Stechele: Dynamically Reconfigurable Systems-on-Chip. Dynamically Reconfigurable Architectures 2006

Andreas Herkersdorf, Walter Stechele: AutoVision: flexible processor architecture for video-assisted driving. DATE 2006: 556

Miljan Vuletic, Paolo Ienne, Christopher Claus, Walter Stechele: Multithreaded virtual-memory-enabled reconfigurable hardware accelerators. FPT 2006: 197-204

Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf: An Architecture for Runtime Evaluation of SoC Reliability. GI Jahrestagung (1) 2006: 177-

Abdelmajid Bouajila, Andreas Bernauer, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele: Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs. BICC 2006: 107-113

Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel: Organic Computing at the System on Chip Level. VLSI-SoC 2006: 338-341

Gabriel Mihai Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele: Towards a Framework and a Design Methodology for Autonomous SoC. ARCS Workshops 2005: 101-108

Walter Stechele, L. Alvado Cárcel, Stephan Herrmann, J. Lidón Simón: A Coprocessor for Accelerating Visual Information Processing. DATE 2005: 26-31

Paul Zuber, Armin Windschiegl, Raúl Medina Beltán de Otálora, Walter Stechele, Andreas Herkersdorf: Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization. DATE 2005: 986-987

Paul Zuber, Florian Helmut Müller, Walter Stechele: Optimization Potential of CMOS Power by Wire Spacing. GI Jahrestagung (1) 2005: 344-348

Gabriel Mihai Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele: Towards a Framework and a Design Methodology for Autonomic SoC. ICAC 2005: 391-392

Paul Zuber, Peter Gritzmann, Michael Ritter, Walter Stechele: The Optimal Wire Order for Low Power CMOS. PATMOS 2005: 674-683

Walter Stechele, Stephan Herrmann, Andreas Herkersdorf: Towards a Dynamically Reconfigurable System-on-Chip Platform for Video Signal Processing. ARCS Workshops 2004: 225-234

Walter Stechele: Performance Optimization of Color Segmentation Algorithms. SIP 2003: 292-297

Ulrich Niedermeier, Jörg Heuer, Andreas Hutter, Walter Stechele: MPEG-7 Binary Format for XML Dat. DCC 2002: 467

Ulrich Niedermeier, Jörg Heuer, Andreas Hutter, Walter Stechele, André Kaup: An MPEG-7 tool for compression and streaming of XML data. ICME (1) 2002: 521-524

Michael Eiermann, Walter Stechele: Novel modeling techniques for RTL power estimation. ISLPED 2002: 323-328

Armin Windschiegl, Paul Zuber, Walter Stechele: Exploiting Metal Layer Characteristics for Low-Power Routing. PATMOS 2002: 55-64

Torsten Mahnke, Walter Stechele, Wolfgang Hoeld: Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment. PATMOS 2002: 146-155

Stephan Herrmann, Hubert Mooshofer, Harald Dietrich, Walter Stechele: A video segmentation algorithm for hierarchical object representations and its implementation. IEEE Trans. Circuits Syst. Video Techn. 9(8): 1204-1215 (1999)

Peter M. Kuhn, Andreas Weisgerber, Robert Poppenwimmer, Walter Stechele: A flexible VLSI architecture for variable block size segment matching with luminance correction. ASAP 1997: 479-488