John Gregory Steffan
List of publications from the DBLP Bibliography Server - FAQ
- CSB - MetaPress - Google - Bing - Yahoo
 | 2012 | |
|---|---|---|
| j9 |      | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose: Portable, Flexible, and Scalable Soft Vector Processors. IEEE Trans. VLSI Syst. 20(8): 1429-1442 (2012) |
| c36 | | Ondrej Lhoták, José Nelson Amaral, Kit Barton, Martin Hirzel, J. Gregory Steffan: 11th Compiler-Driven Performance Workshop. CASCON 2012: 239-240 |
| c35 | | Chuck (Chengyan) Zhao, J. Gregory Steffan, Cristiana Amza, Allan Kielstra: Compiler Support for Fine-Grain Software-Only Checkpointing. CC 2012: 200-219 |
| c34 | | Charles Eric LaForest, Ming G. Liu, Emma Rae Rapati, J. Gregory Steffan: Multi-ported memories for FPGAs via XOR. FPGA 2012: 209-218 |
| c33 | | Charles Eric LaForest, John Gregory Steffan: OCTAVO: an FPGA-centric processor family. FPGA 2012: 219-228 |
| c32 | | Monia Ghobadi, Geoffrey Salmon, Yashar Ganjali, Martin Labrecque, J. Gregory Steffan: Caliper: Precise and Responsive Traffic Generator. Hot Interconnects 2012: 25-32 |
| 2011 | ||
| j8 | | Jeffrey Kingyens, J. Gregory Steffan: The Potential for a GPU-Like Overlay Architecture for FPGAs. Int. J. Reconfig. Comp. 2011 (2011) |
| j7 | | Martin Labrecque, Mark C. Jeffrey, J. Gregory Steffan: Application-specific signatures for transactional memory in soft processors. TRETS 4(3): 21 (2011) |
| c31 | | |
| c30 | | Martin Labrecque, J. Gregory Steffan: NetTM: faster and easier synchronization for soft multicores via transactional memory. FPGA 2011: 29-32 |
| c29 | | Danyao Wang, Natalie D. Enright Jerger, J. Gregory Steffan: DART: A programmable architecture for NoC simulation on FPGAs. NOCS 2011: 145-152 |
| c28 | | Mark C. Jeffrey, J. Gregory Steffan: Understanding bloom filter intersection for lazy address-set disambiguation. SPAA 2011: 345-354 |
| 2010 | ||
| c27 | | Martin Labrecque, J. Gregory Steffan: The case for hardware transactional memory in software packet processing. ANCS 2010: 37 |
| c26 | | Martin Labrecque, Mark C. Jeffrey, J. Gregory Steffan: Application-Specific Signatures for Transactional Memory in Soft Processors. ARC 2010: 42-54 |
| c25 | | Clark Verbrugge, J. Gregory Steffan, Mark G. Stoodley, Kit Barton, Ondrej Lhoták: 9th Workshop on Compiler-Driven Performance. CASCON 2010: 412-413 |
| c24 | | Charles Eric LaForest, J. Gregory Steffan: Efficient multi-ported memories for FPGAs. FPGA 2010: 41-50 |
| c23 | | Steven Birk, J. Gregory Steffan, Jason Helge Anderson: Parallelizing FPGA placement using Transactional Memory. FPT 2010: 61-69 |
| c22 | | Jeffrey Kingyens, J. Gregory Steffan: A GPU-inspired soft processor for high-throughput acceleration. IPDPS Workshops 2010: 1-8 |
| c21 | | Monia Ghobadi, Martin Labrecque, Geoffrey Salmon, Kaveh Aasaraai, Soheil Hassas Yeganeh, Yashar Ganjali, J. Gregory Steffan: Caliper: a tool to generate precise and closed-loop traffic. SIGCOMM 2010: 445-446 |
| e1 |  | Andreas Moshovos, J. Gregory Steffan, Kim M. Hazelwood, David R. Kaeli (Eds.): Proceedings of the CGO 2010, The 8th International Symposium on Code Generation and Optimization, Toronto, Ontario, Canada, April 24-28, 2010. ACM 2010, isbn 978-1-60558-635-9 |
| 2009 | ||
| c20 | | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose: Fine-grain performance scaling of soft vector processors. CASES 2009: 97-106 |
| c19 | | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose: Soft vector processors vs FPGA custom hardware: measuring and reducing the gap. FPGA 2009: 277 |
| c18 | | Martin Labrecque, J. Gregory Steffan: Fast critical sections via thread scheduling for FPGA-based multithreaded processors. FPL 2009: 18-25 |
| c17 | | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose: Data parallel FPGA workloads: Software versus hardware. FPL 2009: 51-58 |
| 2008 | ||
| j6 | | Antonia Zhai, J. Gregory Steffan, Christopher B. Colohan, Todd C. Mowry: Compiler and hardware support for reducing the synchronization of speculative threads. TACO 5(1) (2008) |
| j5 | | Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, Todd C. Mowry: Incrementally parallelizing database transactions with thread-level speculation. ACM Trans. Comput. Syst. 26(1) (2008) |
| c16 | | Mihai Burcea, J. Gregory Steffan, Cristiana Amza: The potential for variable-granularity access tracking for optimistic parallelism. MSPC 2008: 11-15 |
| c15 | | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose: VESPA: portable, scalable, and flexible FPGA-based vector processors. CASES 2008: 61-70 |
| c14 | | Martin Labrecque, Peter Yiannacouras, J. Gregory Steffan: Scaling Soft Processor Systems. FCCM 2008: 195-205 |
| 2007 | ||
| j4 | | Martin Labrecque, Peter Yiannacouras, J. Gregory Steffan: Custom code generation for soft processors. SIGARCH Computer Architecture News 35(3): 9-19 (2007) |
| j3 | | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose: Exploration and Customization of FPGA-Based Soft Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 266-277 (2007) |
| j2 | | Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, Todd C. Mowry: CMP Support for Large and Dependent Speculative Threads. IEEE Trans. Parallel Distrib. Syst. 18(8): 1041-1054 (2007) |
| c13 | | Marek Olszewski, Jeremy Cutler, J. Gregory Steffan: JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory. PACT 2007: 365-375 |
| c12 | | Martin Labrecque, J. Gregory Steffan: Improving Pipelined Soft Processors with Multithreading. FPL 2007: 210-215 |
| 2006 | ||
| c11 | | Jeff Da Silva, J. Gregory Steffan: A probabilistic pointer analysis for speculative optimizations. ASPLOS 2006: 416-425 |
| c10 | | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose: Application-specific customization of soft processor microarchitecture. FPGA 2006: 201-210 |
| c9 | | Stanley L. C. Fung, J. Gregory Steffan: Improving cache locality for thread-level speculation. IPDPS 2006 |
| c8 | | Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, Todd C. Mowry: Tolerating Dependences Between Large Speculative Threads Via Sub-Threads. ISCA 2006: 216-226 |
| 2005 | ||
| j1 | | J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry: The STAMPede approach to thread-level speculation. ACM Trans. Comput. Syst. 23(3): 253-300 (2005) |
| c7 | | Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan: The microarchitecture of FPGA-based soft processors. CASES 2005: 202-212 |
| c6 | | Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, Todd C. Mowry: Optimistic Intra-Transaction Parallelism on Chip Multiprocessors. VLDB 2005: 73-84 |
| 2004 | ||
| c5 | | Antonia Zhai, Christopher B. Colohan, J. Gregory Steffan, Todd C. Mowry: Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads. CGO 2004: 39-52 |
| 2002 | ||
| c4 | | Antonia Zhai, Christopher B. Colohan, J. Gregory Steffan, Todd C. Mowry: Compiler optimization of scalar value communication between speculative threads. ASPLOS 2002: 171-183 |
| c3 | | J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry: Improving Value Communication for Thread-Level Speculation. HPCA 2002: 65-75 |
| 2000 | ||
| c2 | | J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry: A scalable approach to thread-level speculation. ISCA 2000: 1-12 |
| 1998 | ||
| c1 | | J. Gregory Steffan, Todd C. Mowry: The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization. HPCA 1998: 2-13 |
Colors in the list of coauthors
Last update Sun May 19 12:17:43 2013 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page