Per Stenström

Michael J. Flynn, Oskar Mencer, Veljko M. Milutinovic, Goran Rakocevic, Per Stenström, Roman Trobec, Mateo Valero: Moving from petaflops to petadata. Commun. ACM 56(5): 39-42 (2013)

Alen Bardizbanyan, Peter Gavin, David B. Whalley, Magnus Själander, Per Larsson-Edefors, Sally A. McKee, Per Stenström: Improving data access efficiency by using a tagless access buffer (TAB). CGO 2013: 1-11

Per Stenström, Koen De Bosschere: Introduction to the special issue on high-performance and embedded architectures and compilers. TACO 8(4): 18 (2012)

Anurag Negi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Per Stenström: Transactional prefetching: narrowing the window of contention in hardware transactional memory. PACT 2012: 181-190

Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström: π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. HPCA 2012: 141-152

Guancheng Chen, Per Stenström: Critical lock analysis: diagnosing critical section bottlenecks in multithreaded applications. SC 2012: 71

Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García: Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. PACT 2011: 203-204

Mafijul Md. Islam, Per Stenström: A unified approach to eliminate memory accesses early. CASES 2011: 55-64

Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström: Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. ICPP 2011: 73-82

Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström: Implications of Merging Phases on Scalability of Multi-core Architectures. ICPP 2011: 622-631

J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström: ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. ICS 2011: 53-62

Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström: Poster: implications of merging phases on scalability of multi-core architectures. ICS 2011: 380

Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström: The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. IPDPS Workshops 2011: 700-707

Per Stenström, Doug Burger, Wen-mei W. Hwu, Vipin Kumar, Kunle Olukotun, David A. Padua, Burton Smith: Panel Statement. IPDPS 2011: 877

Mridha-Mohammad Waliullah, Per Stenström: Classification and Elimination of Conflicts in Hardware Transactional Memory Systems. SBAC-PAD 2011: 96-103

Per Stenström (Ed.): Transactions on High-Performance Embedded Architectures and Compilers III. Lecture Notes in Computer Science 6590, Springer 2011, isbn 978-3-642-19447-4

Per Stenström (Ed.): Transactions on High-Performance Embedded Architectures and Compilers IV. Lecture Notes in Computer Science 6760, Springer 2011, isbn 978-3-642-24567-1

Yehuda Afek, Ulrich Drepper, Pascal Felber, Christof Fetzer, Vincent Gramoli, Michael Hohmuth, Etienne Riviere, Per Stenström, Osman S. Unsal, Walther Maldonado, Derin Harmanci, Patrick Marlier, Stephan Diestelhorst, Martin Pohlack, Adrián Cristal, Ibrahim Hur, Aleksandar Dragojevic, Rachid Guerraoui, Michal Kapalka, Sasa Tomic, Guy Korland, Nir Shavit, Martin Nowack, Torvald Riegel: The Velox Transactional Memory Stack. IEEE Micro 30(5): 76-87 (2010)

Mafijul Md. Islam, Per Stenström: Characterization and exploitation of narrow-width loads: the narrow-width cache approach. CASES 2010: 227-236

Anurag Negi, M. M. Waliullah, Per Stenström: LV^*: A low complexity lazy versioning HTM infrastructure. ICSAMOS 2010: 231-240

M. M. Waliullah, Per Stenström: Schemes for avoiding starvation in transactional memory systems. Concurrency and Computation: Practice and Experience 21(7): 859-873 (2009)

Per Stenström, David B. Whalley: Introduction. T. HiPEAC 2: 3 (2009)

Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström: FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. Signal Processing Systems 57(1): 5-19 (2009)

Jochen Hollmann, Per Stenström: Using Hoarding to Increase Availability in Shared File Systems. ACIS-ICIS 2009: 422-429

Md. Mafijul Islam, Per Stenström: Zero-Value Caches: Cancelling Loads that Return Zero. PACT 2009: 237-245

Martin Thuresson, Magnus Själander, Per Stenström: A Flexible Code Compression Scheme Using Partitioned Look-Up Tables. HiPEAC 2009: 95-109

Md. Mafijul Islam, Sally A. McKee, Per Stenström: Cancellation of loads that return zero using zero-value caches. ICS 2009: 493-494

Per Stenström (Ed.): Transactions on High-Performance Embedded Architectures and Compilers II. Lecture Notes in Computer Science 5470, Springer 2009, isbn 978-3-642-00903-7

Fredrik Warg, Per Stenström: Dual-thread Speculation: A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor. International Journal of Parallel Programming 36(2): 166-183 (2008)

Jaeheon Jeong, Per Stenström, Michel Dubois: Simple Penalty-Sensitive Cache Replacement Policies. J. Instruction-Level Parallelism 10 (2008)

Md. Mafijul Islam, Magnus Själander, Per Stenström: Early detection and bypassing of trivial operations to improve energy efficiency of processors. Microprocessors and Microsystems - Embedded Hardware Design 32(4): 183-196 (2008)

Martin Thuresson, Lawrence Spracklen, Per Stenström: Memory-Link Compression Schemes: A Value Locality Perspective. IEEE Trans. Computers 57(7): 916-927 (2008)

Reinhard Wilhelm, Jakob Engblom, Andreas Ermedahl, Niklas Holsti, Stephan Thesing, David B. Whalley, Guillem Bernat, Christian Ferdinand, Reinhold Heckmann, Tulika Mitra, Frank Mueller, Isabelle Puaut, Peter P. Puschner, Jan Staschulat, Per Stenström: The worst-case execution-time problem - overview of methods and survey of tools. ACM Trans. Embedded Comput. Syst. 7(3) (2008)

Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström: Leveraging Data Promotion for Low Power D-NUCA Caches. DSD 2008: 307-316

Martin Thuresson, Per Stenström: Accommodation of the Bandwidth of Large Cache Blocks Using Cache/Memory Link Compression. ICPP 2008: 478-486

M. M. Waliullah, Per Stenström: Intermediate checkpointing with conflicting access prediction in transactional memory systems. IPDPS 2008: 1-11

M. M. Waliullah, Per Stenström: Efficient management of speculative data in hardware transactional memory systems. ICSAMOS 2008: 158-164

Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer (Eds.): High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings. Lecture Notes in Computer Science 4917, Springer 2008, isbn 978-3-540-77559-1

Jochen Hollmann, Anders Ardö, Per Stenström: Effectiveness of caching in a distributed digital library system. Journal of Systems Architecture 53(7): 403-416 (2007)

Jianwei Chen, Michel Dubois, Per Stenström: SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators. IEEE Micro 27(4): 34-48 (2007)

M. M. Waliullah, Per Stenström: Starvation-free commit arbitration policies for transactional memory systems. SIGARCH Computer Architecture News 35(1): 39-46 (2007)

Haakon Dybdahl, Per Stenström, Lasse Natvig: An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. SIGARCH Computer Architecture News 35(4): 45-52 (2007)

Alessandro Bardine, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström: Improving power efficiency of D-NUCA caches. SIGARCH Computer Architecture News 35(4): 53-58 (2007)

Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam: High-Performance Embedded Architecture and Compilation Roadmap. T. HiPEAC 1: 5-29 (2007)

Per Stenström: Introduction to Part 1. T. HiPEAC 1: 33 (2007)

Marco Galluzzi, Enrique Vallejo, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero: Implicit Transactional Memory in Kilo-Instruction Multiprocessors. Asia-Pacific Computer Systems Architecture Conference 2007: 339-353

Shekhar Borkar, Norman P. Jouppi, Per Stenström: Microprocessors in the era of terascale integration. DATE 2007: 237-242

M. M. Waliullah, Per Stenström: Starvation-Free Transactional Memory-System Protocols. Euro-Par 2007: 280-291

Haakon Dybdahl, Per Stenström: An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors. HPCA 2007: 2-12

Md. Mafijul Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois, Per Stenström: Loop-level Speculative Parallelism in Embedded Applications. ICPP 2007: 3

Per Stenström: IPDPS Panel: Is the Multi-Core Roadmap going to Live Up to its Promises? IPDPS 2007: 14

Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström: FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. ICSAMOS 2007: 18-25

Md. Mafijul Islam, Per Stenström: Energy and Performance Trade-offs between Instruction Reuse and Trivial Computations for Embedded Applications. SIES 2007: 86-93

Utpal Banerjee, José Moreira, Michel Dubois, Per Stenström (Eds.): Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007. ACM 2007, isbn 978-1-59593-683-7

Koen De Bosschere, David R. Kaeli, Per Stenström, David B. Whalley, Theo Ungerer (Eds.): High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings. Lecture Notes in Computer Science 4367, Springer 2007, isbn 978-3-540-69337-6

Per Stenström, Michael F. P. O'Boyle, François Bodin, Marcelo Cintra, Sally A. McKee (Eds.): Transactions on High-Performance Embedded Architectures and Compilers I. Lecture Notes in Computer Science 4050, Springer 2007, isbn 978-3-540-71527-6

Burkhard Monien, Guang Gao, Horst Simon, Paul G. Spirakis, Per Stenström: Introduction. J. Parallel Distrib. Comput. 66(5): 615-616 (2006)

Haakon Dybdahl, Per Stenström: Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination. Asia-Pacific Computer Systems Architecture Conference 2006: 52-66

Jaeheon Jeong, Per Stenström, Michel Dubois: Simple penalty-sensitive replacement policies for caches. Conf. Computing Frontiers 2006: 341-352

Haakon Dybdahl, Per Stenström, Lasse Natvig: A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors. HiPC 2006: 22-34

Per Stenström: Chip-multiprocessing and beyond. HPCA 2006: 109

Md. Mafijul Islam, Per Stenström: Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations. ICSAMOS 2006: 28-34

Fredrik Warg, Per Stenström: Dual-Thread Speculation: Two Threads in the Machine are Worth Eight in the Bush. SBAC-PAD 2006: 91-98

Martin Thuresson, Per Stenström: Scalable Value-Cache Based Compression Schemes for Multiprocessors. SBAC-PAD 2006: 117-124

Frank Mueller, Per Stenström: Introduction to the special issue. ACM Trans. Embedded Comput. Syst. 4(1): 1-2 (2005)

Martin Thuresson, Per Stenström: Evaluation of extended dictionary-based static code compression schemes. Conf. Computing Frontiers 2005: 77-86

Fredrik Warg, Per Stenström: Reducing misspeculation overhead for module-level speculative execution. Conf. Computing Frontiers 2005: 289-298

Per Stenström: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges. HiPEAC 2005: 5

Magnus Ekman, Per Stenström: A Cost-Effective Main Memory Organization for Future Servers. IPDPS 2005

Magnus Ekman, Per Stenström: A Robust Main-Memory Compression Scheme. ISCA 2005: 74-85

Magnus Ekman, Per Stenström: Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison. ISPASS 2005: 89-99

Håkan Grahn, Per Stenström: A comparative evaluation of hardware-only and software-only directory protocols in shared-memory multiprocessors. Journal of Systems Architecture 50(9): 537-561 (2004)

Jonas Jalminger, Per Stenström: A cache block reuse prediction scheme. Microprocessors and Microsystems 28(7): 373-385 (2004)

Martin Kämpe, Per Stenström, Michel Dubois: Self-correcting LRU replacement policies. Conf. Computing Frontiers 2004: 181-191

Magnus Ekman, Per Stenström: A case for multi-level main memory. WMPI 2004: 1-8

Jochen Hollmann, Anders Ardö, Per Stenström: An Evaluation of Document Prefetching in a Distributed Digital Library. ECDL 2003: 276-287

Per Stenström: One Chip, One Server: How Do We Exploit Its Power? HiPC 2003: 405

Jonas Jalminger, Per Stenström: A Novel Approach to Cache Block Reuse Predictions. ICPP 2003: 294-

Magnus Ekman, Per Stenström: Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores. ICPP 2003: 359-368

Jim Nilsson, Anders Landin, Per Stenström: The Coherence Predictor Cache: A Resource-Efficient and Accurate Coherence Prediction Infrastructure. IPDPS 2003: 10

Peter Rundberg, Per Stenström: Speculative Lock Reordering: Optimistic Out-of-Order Execution of Critical Sections. IPDPS 2003: 11

Fredrik Warg, Per Stenström: Improving Speculative Thread-Level Parallelism Through Module Run-Length Prediction. IPDPS 2003: 12

Jianwei Chen, Michel Dubois, Per Stenström: Integrating complete-system and user-level performance/power simulators: the SimWattch approach. ISPASS 2003: 1-10

Jonas Jalminger, Per Stenström: Improvement of energy-efficiency in off-chip caches by selective prefetching. Microprocessors and Microsystems 26(3): 107-121 (2002)

Martin Kämpe, Per Stenström, Michel Dubois: The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches. HPCA 2002: 223-232

Jochen Hollmann, Anders Ardö, Per Stenström: Empirical Observations Regarding Predictability in User Access-Behavior in a Distributed Digital Library System. IPDPS 2002

Magnus Ekman, Per Stenström, Fredrik Dahlgren: TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. ISLPED 2002: 243-246

Peter Rundberg, Per Stenström: An All-Software Thread-Level Data Dependence Speculation System for Multiprocessors. J. Instruction-Level Parallelism 3 (2001)

Fredrik Warg, Per Stenström: Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms. IEEE PACT 2001: 221-230

Ulf Assarsson, Per Stenström: A Case Study of Load Distribution in Parallel View Frustum Culling and Collision Detection. Euro-Par 2001: 663-673

Per Stenström (Ed.): Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, Göteborg, Sweden, June 30-July 4, 2001. ACM 2001, isbn 0-7695-1162-7

Per Stenström, Erik Hagersten, David J. Lilja, Margaret Martonosi, Madan Venugopal: Shared-memory multiprocessing: Current state and future directions. Advances in Computers 53: 1-53 (2000)

Håkan Grahn, Per Stenström: Comparative Evaluation of Latency-Tolerating and -Reducing Techniques for Hardware-Only and Software-Only Directory Protocols. J. Parallel Distrib. Comput. 60(7): 807-834 (2000)

Silvia M. Müller, Per Stenström, Mateo Valero, Stamatis Vassiliadis: Parallel Computer Architecture. Euro-Par 2000: 537-538

Magnus Karlsson, Fredrik Dahlgren, Per Stenström: A Prefetching Technique for Irregular Accesses to Linked Data Structures. HPCA 2000: 206-217

Ashley Saulsbury, Fredrik Dahlgren, Per Stenström: Recency-based TLB preloading. ISCA 2000: 117-127

Magnus Karlsson, Per Stenström: An analytical model of the working-set sizes in decision-support systems. SIGMETRICS 2000: 275-285

Jonas Skeppstedt, Fredrik Dahlgren, Per Stenström: Evaluation of Compiler-Controlled Updating to Reduce Coherence-Miss Penalties in Shared-Memory Multiprocessors. J. Parallel Distrib. Comput. 56(2): 122-143 (1999)

Thomas Lundqvist, Per Stenström: An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution. Real-Time Systems 17(2-3): 183-207 (1999)

Thomas Lundqvist, Per Stenström: A Method to Improve the Estimated Worst-Case Performance of Data Caching. RTCSA 1999: 255-262

Thomas Lundqvist, Per Stenström: Timing Anomalies in Dynamically Scheduled Microprocessors. RTSS 1999: 12-21

Fredrik Dahlgren, Michel Dubois, Per Stenström: Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors. IEEE Trans. Computers 47(10): 1041-1055 (1998)

Thomas Lundqvist, Per Stenström: Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques. LCTES 1998: 1-15

Fredrik Dahlgren, Per Stenström, Mårten Björkman: Reducing the Read-Miss Penalty for Flat COMA Protocols. Comput. J. 40(4): 208-219 (1997)

Per Stenström, Mats Brorsson, Fredrik Dahlgren, Håkan Grahn, Michel Dubois: Boosting the Performance of Shared Memory Multiprocessors. IEEE Computer 30(7): 63-70 (1997)

Per Stenström, Erik Hagersten, David J. Lilja, Margaret Martonosi, Madan Venugopal: Trends in Shared Memory Multiprocessing. IEEE Computer 30(12): 44-50 (1997)

Magnus Karlsson, Per Stenström: Effectivness of Dynamic Prefetching in Multiple-Writer Distributed Virtual Shared-Memory Systems. J. Parallel Distrib. Comput. 43(2): 79-93 (1997)

Per Stenström, Jonas Skeppstedt: A Performance Tuning Approach for Shared-Memory Multiprocessors. Euro-Par 1997: 72-83

Håkan Grahn, Per Stenström: Relative Performance of Hardware and Software-Only Directory Protocols Under Latency Tolerating and Reducing Techniques. IPPS 1997: 500-

Per Stenström, Fredrik Dahlgren: Applications for Shared Memory Multiprocessors (Guest Editors' Introduction). IEEE Computer 29(12): 29-31 (1996)

Håkan Grahn, Per Stenström: Evaluation of a Competitive-Update Cache Coherence Protocol with Migratory Data Detection. J. Parallel Distrib. Comput. 39(2): 168-180 (1996)

Mats Brorsson, Per Stenström: Characterising and Modelling Shared Memory Accesses in Multiprocessor Programs. Parallel Computing 22(6): 869-893 (1996)

Jonas Skeppstedt, Per Stenström: Using Dataflow Analysis Techniques to Reduce Ownership Overhead in Cache Coherence Protocols. ACM Trans. Program. Lang. Syst. 18(6): 659-682 (1996)

Fredrik Dahlgren, Per Stenström: Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. IEEE Trans. Parallel Distrib. Syst. 7(4): 385-398 (1996)

Magnus Karlsson, Per Stenström: Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers. HPCA 1996: 4-13

Fredrik Dahlgren, Per Stenström: Using Write Caches to Improve Performance of Cache Coherence Protocols in Shared-Memory Multiprocessors. J. Parallel Distrib. Comput. 26(2): 193-210 (1995)

Michel Dubois, Jonas Skeppstedt, Per Stenström: Essential Misses and Data Traffic in Coherence Protocols. J. Parallel Distrib. Comput. 29(2): 108-125 (1995)

Fredrik Dahlgren, Michel Dubois, Per Stenström: Sequential Hardware Prefetching in Shared-Memory Multiprocessors. IEEE Trans. Parallel Distrib. Syst. 6(7): 733-746 (1995)

Mårten Björkman, Fredrik Dahlgren, Per Stenström: Using hints to reduce the read miss penalty for flat COMA protocols. HICSS (1) 1995: 242-251

Fredrik Dahlgren, Per Stenström: Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. HPCA 1995: 68-77

Håkan Grahn, Per Stenström: Efficient Strategies for Software-Only Protocols in Shared-Memory Multiprocessors. ISCA 1995: 38-47

Jonas Skeppstedt, Per Stenström: Simple Compiler Algorithms to Reduce Ownership Operhead in Cache Coherence Protocols. ASPLOS 1994: 286-296

Per Stenström: Introduction. HICSS (1) 1994: 520-521

Fong Pong, Per Stenström, Michel Dubois: An Integrated Methodology for the Verification of Directory-Based Cache Protocols. ICPP (1) 1994: 158-165

Fredrik Dahlgren, Per Stenström: Reducing the Write Traffic for a Hybrid Cache Protocol. ICPP (1) 1994: 166-173

Fredrik Dahlgren, Michel Dubois, Per Stenström: Combined Performance Gains of Simple Cache Protocol Extensions. ISCA 1994: 187-197

Håkan Nilsson, Per Stenström: An Adaptive Update-Based Cache Coherence Protocol for Reduction of Miss Rate and Traffic. PARLE 1994: 363-374

Fredrik Dahlgren, Michel Dubois, Per Stenström: Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. ICPP 1993: 56-63

Michel Dubois, Jonas Skeppstedt, Livio Ricciulli, Krishnan Ramamurthy, Per Stenström: The Detection and Elimination of Useless Misses in Multiprocessors. ISCA 1993: 88-97

Per Stenström, Mats Brorsson, Lars Sandberg: An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing. ISCA 1993: 109-118

Per Stenström: A Latency-Hiding Scheme for Multiprocessors with Buffered Multistage Networks. IPPS 1992: 39-42

Per Stenström, Truman Joe, Anoop Gupta: Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures. ISCA 1992: 80-91

Håkan Nilsson, Per Stenström: The Scalable Tree Protocol - A Cache Coherence Approach for Large-Scale Multiprocessors. SPDP 1992: 498-506

Per Stenström, Fredrik Dahlgren, Lars Lundberg: A Lockup-Free Multiprocessor Cache Design. ICPP (1) 1991: 246-250

Fredrik Dahlgren, Per Stenström: On Reconfigurable On-Chip Data Caches. MICRO 1991: 189-198

Per Stenström: A Survey of Cache Coherence Schemes for Multiprocessors. IEEE Computer 23(6): 12-24 (1990)

Per Stenström: A Cache Consistency Protocol for Multiprocessors with Multistage Networks. ISCA 1989: 407-415

Per Stenström: Reducing Contention in Sharde-Memory Multiprocessors. IEEE Computer 21(11): 26-37 (1988)

Per Stenström, Lars Philipson: A Layered Emulator for Design Evaluation of MIMD Multiprocessors with Shared Memory. PARLE (1) 1987: 329-344