- CSB - MetaPress - Google - Bing - Yahoo
 | 1997 | |
|---|---|---|
| c21 |      | Stephen Y. H. Su, Rong Yao: Fault-Tolerant Array Processors Via Reconfiguration of Two-Level Redundancy Arrays. PDPTA 1997: 1633-1642 |
| 1991 | ||
| j16 |  | Stephen Y. H. Su, Michal Cutler, Mingshien Wang: Self-Diagnosis of Faelures in VLSI Tree Array Processors. IEEE Trans. Computers 40(11): 1252-1257 (1991) |
| 1989 | ||
| j15 | | Mingshien Wang, Michal Cutler, Stephen Y. H. Su: Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy. IEEE Trans. Computers 38(4): 547-554 (1989) |
| 1988 | ||
| j14 | | Li Shen, Stephen Y. H. Su: A Functional Testing Method for Microprocessors. IEEE Trans. Computers 37(10): 1288-1293 (1988) |
| c20 | | |
| c19 | | |
| 1986 | ||
| j13 | | Israel Koren, Zahava Koren, Stephen Y. H. Su: Analysis of a Class of Recovery Procedures. IEEE Trans. Computers 35(8): 703-712 (1986) |
| 1985 | ||
| j12 | | Shiyi Xu, Stephen Y. H. Su: Detecting I/O and Internal Feedback Bridging Faults. IEEE Trans. Computers 34(6): 553-557 (1985) |
| j11 | | Tonysheng Lin, Stephen Y. H. Su: The S-Algorithm: A Promising Solution for Systematic Functional Test Generation. IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 250-263 (1985) |
| c18 | | Tonysheng Lin, Stephen Y. H. Su: VLSI Functional Test Pattern Generation: A Design and Implementation. ITC 1985: 922-929 |
| 1984 | ||
| c17 | | Stephen Y. H. Su: IDAS: an integrated design automation system. AFIPS National Computer Conference 1984: 143-150 |
| c16 | | Stephen Y. H. Su, Tonysheng Lin: Functional testing techniques for digital LSI/VLSI systems. DAC 1984: 517-528 |
| c15 | | Li Shen, Stephen Y. H. Su: VLSI functional testing using critical path traces at hardware description language level. Fehlertolerierende Rechensysteme 1984: 364-379 |
| c14 | | Tonysheng Lin, Stephen Y. H. Su: Functional Test Generation of Digital LSI/VLSI Systems Using Machine Symbolic Execution Technique. ITC 1984: 660-668 |
| 1983 | ||
| c13 | | Kewal K. Saluja, Li Shen, Stephen Y. H. Su: A Simplified Algorithm for Testing Microprocessors. ITC 1983: 668-675 |
| 1982 | ||
| j10 | | Yacoub M. El-Ziq, Stephen Y. H. Su: Fault Diagnosis of MOS Combinational Networks. IEEE Trans. Computers 31(2): 129-139 (1982) |
| c12 | | |
| c11 | | Yashwant K. Malaiya, Stephen Y. H. Su: A New Fault Model and Testing Technique for CMOS Devices. ITC 1982: 25-34 |
| 1981 | ||
| j9 | | Yashwant K. Malaiya, Stephen Y. H. Su: Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults. IEEE Trans. Computers 30(8): 600-604 (1981) |
| j8 | | Chi-Chang Liaw, Stephen Y. H. Su, Yashwant K. Malaiya: Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits. IEEE Trans. Computers 30(12): 989-995 (1981) |
| c10 | | Chi-Chang Liaw, Stephen Y. H. Su, Yashwant K. Malaiya: State Diagram Approach for Functional Testing of Control Section. ITC 1981: 433-446 |
| c9 | | Stephen Y. H. Su, Yu-I Hsieh: Testing Functional Faults in Digital Systems Described by Register Transfer Language. ITC 1981: 447-457 |
| 1980 | ||
| j7 | | Stephen Y. H. Su, Edgar DuCasse: A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures. IEEE Trans. Computers 29(3): 254-258 (1980) |
| j6 | | Mark G. Karpovsky, Stephen Y. H. Su: Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines. IEEE Trans. Computers 29(6): 523-527 (1980) |
| c8 | | Mark G. Karpovsky, Stephen Y. H. Su: Detecting bridging and stuck-at faults at input and output pins of standard digital components. DAC 1980: 494-505 |
| 1979 | ||
| j5 | | Israel Koren, Stephen Y. H. Su: Reliability Analysis of N-Modular Redundancy Systems with Intermittent and Permanent Faults. IEEE Trans. Computers 28(7): 514-520 (1979) |
| 1978 | ||
| j4 | | Stephen Y. H. Su, Israel Koren, Yashwant K. Malaiya: A Continous-Parameter Markov Model and Detection Procedures for Intermittent Faults. IEEE Trans. Computers 27(6): 567-570 (1978) |
| j3 | | Yacoub M. El-Ziq, Stephen Y. H. Su: Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results. IEEE Trans. Computers 27(10): 911-923 (1978) |
| 1977 | ||
| j2 | | Richard J. Spillman, Stephen Y. H. Su: Detection of Single, Stuck-Type Faulures in Multivalued Combinational Networks. IEEE Trans. Computers 26(12): 1242-1251 (1977) |
| c7 | | Stephen Y. H. Su, Richard J. Spillman: An overview of fault-tolerant digital system architecture. AFIPS National Computer Conference 1977: 19-26 |
| c6 | | Yacoub M. El-Ziq, Stephen Y. H. Su: Logic design automation of diagnosable MOS combinational logic networks. DAC 1977: 205-215 |
| 1976 | ||
| j1 | | Melvin A. Breuer, Shih-Jeh Chang, Stephen Y. H. Su: Identification of Multiple Stuck-Type Faults in Combinational Networks. IEEE Trans. Computers 25(1): 44-54 (1976) |
| 1974 | ||
| c5 | | |
| 1973 | ||
| c4 | | |
| 1971 | ||
| c3 | | Mehmet Baray, Stephen Y. H. Su: A digital system modeling philosophy and design language. DAC 1971: 1-22 |
| c2 | | Mehmet Baray, Stephen Y. H. Su, Robert L. Carberry: The structure and operation of a design language compatible simulator. DAC 1971: 23-34 |
| c1 | | Stephen Y. H. Su, Mehmet Baray, Robert L. Carberry: A system modeling language translator. DAC 1971: 35-49 |
Colors in the list of coauthors
Last update Sun May 19 03:47:00 2013 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page