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 | 2012 | |
|---|---|---|
| j6 |      | Chuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee: Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates. IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1698-1710 (2012) |
| c10 | | Zohaib Mahmood, Roberto Suaya, Luca Daniel: An efficient framework for passive compact dynamical modeling of multiport linear systems. DATE 2012: 1203-1208 |
| 2010 | ||
| j5 | | Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee: Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060]. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 849 (2010) |
| c9 | | Navin Srivastava, Roberto Suaya, Kaustav Banerjee: Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. DATE 2010: 459-464 |
| 2009 | ||
| j4 | | Navin Srivastava, Roberto Suaya, Kaustav Banerjee: Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate. IEEE Trans. on CAD of Integrated Circuits and Systems 28(7): 1047-1060 (2009) |
| 2008 | ||
| c8 | | Navin Srivastava, Roberto Suaya, Kaustav Banerjee: High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. DATE 2008: 426-431 |
| 2007 | ||
| c7 | | Salvador Ortiz, Roberto Suaya: Efficient implementation of conduction modes for modelling skin effect. ISVLSI 2007: 500-505 |
| 2006 | ||
| c6 | | Salvador Ortiz, Roberto Suaya: Fullwave volumetric Maxwell solver using conduction modes. ICCAD 2006: 13-18 |
| c5 | | Rafael Escovar, Salvador Ortiz, Roberto Suaya: Mutual inductance between intentional inductors: closed form expressions. ISCAS 2006 |
| 2005 | ||
| j3 | | Rafael Escovar, Salvador Ortiz, Roberto Suaya: An improved long distance treatment for mutual inductance. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 783-793 (2005) |
| c4 | | Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen: Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? ASP-DAC 2005 |
| 2004 | ||
| j2 | | Rafael Escovar, Roberto Suaya: Optimal design of clock trees for multigigahertz applications. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 329-345 (2004) |
| c3 | | Rafael Escovar, Salvador Ortiz, Roberto Suaya: Mutual inductance extraction and the dipole approximation. ISPD 2004: 162-169 |
| 2002 | ||
| c2 | | |
| 1991 | ||
| c1 | | Paul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya: A Two-Dimensional Topological Compactor With Octagonal Geometry. DAC 1991: 727-731 |
| 1990 | ||
| j1 | | John Valainis, Sinan Kaptanoglu, Erwin Liu, Roberto Suaya: Two-dimensional IC layout compaction based on topological design rule checking. IEEE Trans. on CAD of Integrated Circuits and Systems 9(3): 260-275 (1990) |
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