Susmita Sur-Kolay

Debasri Saha, Susmita Sur-Kolay: Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol. IEEE Trans. VLSI Syst. 20(10): 1749-1757 (2012)

Susmita Sur-Kolay: Intellectual property protection and security of SoCs - An embedded tutorial. SoCC 2012: 289

Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay: A Synthesis Method for Quaternary Quantum Logic Circuits. VDAT 2012: 270-280

Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal: A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts. VDAT 2012: 327-336

Susmita Sur-Kolay, Swarup Bhunia: Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design. VLSI Design 2012: 18-19

Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay: A Synthesis Method for Quaternary Quantum Logic Circuits. CoRR abs/1210.8055 (2012)

Pritha Banerjee, Debasri Saha, Susmita Sur-Kolay: Cone-based placement for field programmable gate arrays. IET Computers & Digital Techniques 5(1): 49-62 (2011)

Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay: Floorplanning for Partially Reconfigurable FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(1): 8-17 (2011)

Debasri Saha, Susmita Sur-Kolay: SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection. VLSI Design 2011 (2011)

Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay: Synthesis Techniques for Ternary Quantum Logic. ISMVL 2011: 218-223

Ayan Datta, Charudhattan Nagarajan, Susmita Sur-Kolay: TSV-aware Scan Chain Reordering for 3D IC. ISVLSI 2011: 188-193

Amlan Chakrabarti, Susmita Sur-Kolay, Ayan Chaudhury: Linear Nearest Neighbor Synthesis of Reversible Circuits by Graph Partitioning. CoRR abs/1112.0564 (2011)

Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sandip Kundu, Ashish Nigam, Sandeep K. Dey: Test pattern generation for droop faults. IET Computers & Digital Techniques 4(4): 274-284 (2010)

Debasri Saha, Susmita Sur-Kolay: Robust intellectual property protection of VLSI physical design. IET Computers & Digital Techniques 4(5): 388-399 (2010)

Debasri Saha, Susmita Sur-Kolay: A Unified Approach for IP Protection across Design Phases in a Packaged Chip. VLSI Design 2010: 105-110

Sriparna Saha, Susmita Sur-Kolay, Parthasarathi Dasgupta, Sanghamitra Bandyopadhyay: MAkE: Multiobjective algorithm for k-way equipartitioning of a point set. Appl. Soft Comput. 9(2): 711-724 (2009)

Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya: Droop sensitivity of stuck-at fault tests. IET Computers & Digital Techniques 3(2): 175-193 (2009)

Susmita Sur-Kolay, Satyajit Banerjee, S. Mukhopadhyaya, C. A. Murthy: The Double Digest Problem: finding all solutions. IJBRA 5(5): 570-592 (2009)

Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu: Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 651-661 (2009)

Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu, Sandip Das, Subhas C. Nandy, Subhasis Bhattacharjee: FPGA placement using space-filling curves: Theory meets practice. ACM Trans. Embedded Comput. Syst. 9(2) (2009)

Debasri Saha, Susmita Sur-Kolay: Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design. ISVLSI 2009: 169-174

Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay: Floorplanning for Partial Reconfiguration in FPGAs. VLSI Design 2009: 125-130

Debasri Saha, Susmita Sur-Kolay: Encoding of Floorplans through Deterministic Perturbation. VLSI Design 2009: 315-320

Amlan Chakrabarti, Susmita Sur-Kolay: Nearest Neighbour based Synthesis of Quantum Boolean Circuits. Engineering Letters 15(2): 356-361 (2007)

Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das: Hierarchical partitioning of VLSI floorplans by staircases. ACM Trans. Design Autom. Electr. Syst. 12(1) (2007)

Debasri Saha, Susmita Sur-Kolay: Fast Robust Intellectual Property Protection for VLSI Physical Design. ICIT 2007: 1-6

Debasri Saha, Parthasarathi Dasgupta, Susmita Sur-Kolay, Samar Sen-Sarma: A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection. ICCTA 2007: 111-116

Pritha Banerjee, Susmita Sur-Kolay: Faster Placer for Island-Style FPGAs. ICCTA 2007: 117-121

Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu: Floorplanning in Modern FPGAs. VLSI Design 2007: 893-898

Sriparna Saha, Susmita Sur-Kolay, Sanghamitra Bandyopadhyay, Parthasarathi Dasgupta: Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI. ICIT 2006: 281-284

Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu: Test Pattern Generation for Power Supply Droop Faults. VLSI Design 2006: 343-348

Pritha Banerjee, Subhasis Bhattacharjee, Susmita Sur-Kolay, Sandip Das, Subhas C. Nandy: Fast FPGA Placement using Space-filling Curve. FPL 2005: 415-420

Susmita Sur-Kolay, Satyajit Banerjee, S. Mukhopadhyaya, C. A. Murthy: Genetic Algorithm for Double Digest Problem. PReMI 2005: 623-629

Subhashis Majumder, Susmita Sur-Kolay, Subhas C. Nandy, Bhargab B. Bhattacharya, B. Chakraborty: Hot Spots and Zones in a Chip: A Geometrician's View. VLSI Design 2005: 691-696

Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya: Manhattan-diagonal routing in channels and switchboxes. ACM Trans. Design Autom. Electr. Syst. 9(1): 75-104 (2004)

Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang: A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. DATE 2004: 1078-1083

Sanjay Goswami, Susmita Sur-Kolay: Virtual Molecular Computing - Emulating DNA Molecules. IWDC 2004: 95-101

Susmita Sur-Kolay, Parthasarathi Dasgupta, Bhargab B. Bhattacharya, Sujit T. Zachariah: Physical Design Trends and Layout-Based Fault Modeling. VLSI Design 2004: 6-8

Susmita Sur-Kolay, Satyajit Banerjee, C. A. Murthy: Flavours of Traveling Salesman Problem in VLSI Design. IICAI 2003: 656-667

Parthasarathi Dasgupta, Susmita Sur-Kolay: Slicible rectangular graphs and their optimal floorplans. ACM Trans. Design Autom. Electr. Syst. 6(4): 447-470 (2001)

Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay: Combining Instruction and Loop Level Parallelism for FPGAs. FCCM 2001: 273-282

Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Subhas C. Nandy: Area(number)-balanced hierarchy of staircase channels with minimum crossing nets. ISCAS (5) 2001: 395-398

Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay: Combined instruction and loop parallelism in array synthesis for FPGAs. ISSS 2001: 165-170

Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta: Partitioning Routing Area into Zones with Distinct Pins. VLSI Design 2001: 345-

Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy: Fsimac: a fault simulator for asynchronous sequential circuits. Asian Test Symposium 2000: 114-119

Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay: Optimal Partitioning for FPGA Based Regular Array Implementations. PARELEC 2000: 155-159

Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya: Topological Routing Amidst Polygonal Obstacles. VLSI Design 2000: 274-279

Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya: A unified approach to topology generation and optimal sizing of floorplans. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 126-135 (1998)

Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya: Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model. VLSI Design 1998: 65-

Parthasarathi Dasgupta, Susmita Sur-Kolay: Slicibility of rectangular graphs and floorplan optimization. ISPD 1997: 150-155

Abhik Roychoudhury, Susmita Sur-Kolay: Efficient Algorithms for Vertex Arboricity of Planar Graphs. FSTTCS 1995: 37-51

Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya: A unified approach to topology generation and area optimization of general floorplans. ICCAD 1995: 712-715

P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya: VLSI floorplan generation and area optimization using AND-OR graph search. VLSI Design 1995: 370-375

Susmita Sur-Kolay, Bhargab B. Bhattacharya: Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning. DAC 1992: 69-74

Susmita Sur-Kolay, Bhargab B. Bhattacharya: The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order. ICCD 1991: 524-527

Susmita Sur-Kolay, Bhargab B. Bhattacharya: Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning. FSTTCS 1988: 88-107