Gustavo Sutter

Diego Sanchez-Roman, Victor Moreno, Sergio López-Buedo, Gustavo Sutter, Ivan Gonzalez, Francisco J. Gomez-Arribas, Javier Aracil: FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options. Journal of Systems Architecture - Embedded Systems Design 59(3): 135-143 (2013)

Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña: Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations. IEEE Transactions on Industrial Electronics 60(1): 217-225 (2013)

Jean-Pierre Deschamps, Gustavo Sutter, Enrique Cantó: Guide to FPGA Implementation of Arithmetic Functions. Lecture Notes in Electrical Engineering 149, Springer 2012, isbn 978-94-007-2986-5, pp. 1-459

Ivan Gonzalez, Sergio López-Buedo, Gustavo Sutter, Diego Sanchez-Roman, Francisco J. Gomez-Arribas, Javier Aracil: Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture. Journal of Systems Architecture - Embedded Systems Design 58(6-7): 247-256 (2012)

Diego Sanchez-Roman, Gustavo Sutter, Sergio López-Buedo, Ivan Gonzalez, Francisco J. Gomez-Arribas, Javier Aracil, Francisco Palacios: High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations. IEEE Design & Test of Computers 28(4): 28-37 (2011)

Elias Todorovich, Gustavo Sutter: Selected Papers from the Southern Programmable Logic Conference (SPL2010). Int. J. Reconfig. Comp. 2011 (2011)

Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña: Modular Multiplication and Exponentiation Architectures for Fast RSA Cryptosystem Based on Digit Serial Computation. IEEE Transactions on Industrial Electronics 58(7): 3101-3109 (2011)

Gery Bioul, Martín Vazquez, Jean-Pierre Deschamps, Gustavo Sutter: High-Speed FPGA 10's Complement Adders-Subtractors. Int. J. Reconfig. Comp. 2010 (2010)

Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña: Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation. FPL 2010: 496-501

Gustavo Sutter, Jean-Pierre Deschamps: High speed fixed point dividers for FPGAs. FPL 2009: 448-452

Gustavo Sutter, Elias Todorovich, Gery Bioul, Martín Vazquez, Jean-Pierre Deschamps: FPGA Implementations of BCD Multipliers. ReConFig 2009: 36-41

Martín Vazquez, Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps: Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations. ReConFig 2009: 42-47

Carlos Minchola, Gustavo Sutter: A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier. ReConFig 2009: 59-64

Gustavo Sutter, Richard Katz: Selected Papers from SPL 2008: Programmable Logic and Applications. Int. J. Reconfig. Comp. 2008 (2008)

Jean-Pierre Deschamps, Gustavo Sutter: Finite Field Division Implementation. FPL 2005: 670-674

Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps: Comparative Study of SRT-Dividers in FPGA. FPL 2004: 209-220

Gustavo Sutter, Jean-Pierre Deschamps, Gery Bioul, Eduardo I. Boemo: Power Aware Dividers in FPGA. PATMOS 2004: 574-584

Elias Todorovich, M. Gilabert, Gustavo Sutter, Sergio López-Buedo, Eduardo I. Boemo: A Tool for Activity Estimation in FPGAs. FPL 2002: 340-349

Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo: FSM Decomposition for Low Power in FPGA. FPL 2002: 350-359

Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo: Low-Power FSMs in FPGA: Encoding Alternatives. PATMOS 2002: 363-370