Earl E. Swartzlander Jr.

Liang Lu, Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.: QCA Systolic Array Design. IEEE Trans. Computers 62(3): 548-560 (2013)

Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan: Structure-Aware Placement Techniques for Designs With Datapaths. IEEE Trans. on CAD of Integrated Circuits and Systems 32(2): 228-241 (2013)

Hyesook Lim, Soohyun Lee, Earl E. Swartzlander Jr.: A new hierarchical packet classification algorithm. Computer Networks 56(13): 3010-3022 (2012)

Earl E. Swartzlander Jr., Hani Saleh: FFT Implementation with Fused Floating-Point Operations. IEEE Trans. Computers 61(2): 284-288 (2012)

Jongwook Sohn, Earl E. Swartzlander Jr.: Improved Architectures for a Fused Floating-Point Add-Subtract Unit. IEEE Trans. on Circuits and Systems 59-I(10): 2285-2291 (2012)

Michael B. Sullivan, Earl E. Swartzlander Jr.: Long Residue Checking for Adders. ASAP 2012: 177-180

Weiqiang Liu, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.: Cost-efficient decimal adder design in Quantum-dot cellular automata. ISCAS 2012: 1347-1350

Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan: Keep it straight: teaching placement how to better handle designs with datapaths. ISPD 2012: 79-86

Inwook Kong, Earl E. Swartzlander Jr.: A Goldschmidt Division Method With Faster Than Quadratic Convergence. IEEE Trans. VLSI Syst. 19(4): 696-700 (2011)

Waqas Akram, Earl E. Swartzlander Jr.: Tunable Mismatch Shaping for Quadrature Bandpass Delta-Sigma Data Converters. Signal Processing Systems 65(2): 199-210 (2011)

Weiqiang Liu, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.: Design rules for Quantum-dot Cellular Automata. ISCAS 2011: 2361-2364

Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.: Quantifying academic placer performance on custom designs. ISPD 2011: 91-98

Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca (Eds.): 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011. IEEE 2011, isbn 978-1-4577-1291-3

Terence K. Rodrigues, Earl E. Swartzlander Jr.: Adaptive CORDIC: Using Parallel Angle Recoding to Accelerate Rotations. IEEE Trans. Computers 59(4): 522-531 (2010)

Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr.: Priority Tries for IP Address Lookup. IEEE Trans. Computers 59(6): 784-794 (2010)

Ron S. Waters, Earl E. Swartzlander Jr.: A Reduced Complexity Wallace Multiplier Reduction. IEEE Trans. Computers 59(8): 1134-1137 (2010)

Inwook Kong, Earl E. Swartzlander Jr.: A Rounding Method to Reduce the Required Multiplier Precision for Goldschmidt Division. IEEE Trans. Computers 59(12): 1703-1708 (2010)

Waqas Akram, Earl E. Swartzlander Jr.: A novel technique for tunable mismatch shaping in oversampled digital-to-analog converters. ICASSP 2010: 1534-1537

Liang Lu, Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.: QCA Systolic Matrix Multiplier. ISVLSI 2010: 149-154

Shakeel S. Abdulla, Haewoon Nam, Earl E. Swartzlander Jr., Jacob A. Abraham: High speed recursion-free CORDIC architecture. SoCC 2010: 65-70

Heumpil Cho, Earl E. Swartzlander Jr.: Adder and Multiplier Design in Quantum-Dot Cellular Automata. IEEE Trans. Computers 58(6): 721-727 (2009)

Bassam Jamil Mohd, Earl E. Swartzlander Jr.: A Power-Scalable Switch-Based Multi-processor FFT. ASAP 2009: 114-120

Robert J. Ascott, Earl E. Swartzlander Jr.: JavaFlow - A Java dataflow machine. SoCC 2009: 211-214

Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.: ASIC evaluation of ECHO hash function. SoCC 2009: 387-390

Youngmoon Choi, Earl E. Swartzlander Jr.: Speculative Carry Generation With Prefix Adder. IEEE Trans. VLSI Syst. 16(3): 321-326 (2008)

Eric Quinnell, Earl E. Swartzlander Jr., Carl Lemonds: Bridge Floating-Point Fused Multiply-Add Design. IEEE Trans. VLSI Syst. 16(12): 1727-1731 (2008)

Robert T. Grisamore, Earl E. Swartzlander Jr.: Negative Save Sign Extension for Multi-term Adders and Multipliers. Signal Processing Systems 52(1): 1-11 (2008)

Earl E. Swartzlander Jr.: Systolic FFT Processors: A Personal Perspective. Signal Processing Systems 53(1-2): 3-14 (2008)

Vijay K. Jain, Earl E. Swartzlander Jr.: 32 bit single cycle nonlinear VLSI cell for the ICA algorithm. ICASSP 2008: 1429-1432

Hani Saleh, Earl E. Swartzlander Jr.: A floating-point fused dot-product unit. ICCD 2008: 427-431

Xin Yang, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr.: High performance IP lookup circuit using DDR SDRAM. SoCC 2008: 371-374

Eric Quinnell, Earl E. Swartzlander Jr.: Floating-Point Computer Arithmetic. Wiley Encyclopedia of Computer Science and Engineering 2008

Earl E. Swartzlander Jr.: Fixed-Point Computer Arithmetic. Wiley Encyclopedia of Computer Science and Engineering 2008

Earl E. Swartzlander Jr.: The Negative Two's Complement Number System. VLSI Signal Processing 49(1): 177-183 (2007)

Heumpil Cho, Earl E. Swartzlander Jr.: Serial Parallel Multiplier Design in Quantum-dot Cellular Automata. IEEE Symposium on Computer Arithmetic 2007: 7-15

Hani Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.: Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. ICCD 2007: 7-12

Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.: The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. VLSI-SoC 2007: 194-199

Tung N. Pham, Earl E. Swartzlander Jr.: Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology. ASAP 2006: 105-108

Earl E. Swartzlander Jr.: Systolic FFT Processors: Past, Present and Future. ASAP 2006: 153-158

Youngmoon Choi, Earl E. Swartzlander Jr.: Parallel Prefix Adder Design with Matrix Representation. IEEE Symposium on Computer Arithmetic 2005: 90-98

Moboluwaji O. Sanu, Earl E. Swartzlander Jr.: Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields. ASAP 2005: 134-139

Earl E. Swartzlander Jr.: Three Dimensional System on Chip Technology, invited. IWSOC 2005: 465-470

Moboluwaji O. Sanu, Earl E. Swartzlander Jr., Craig M. Chase: Parallel Montgomery Multipliers. ASAP 2004: 63-72

Earl E. Swartzlander Jr.: A Review of Large Parallel Counter Designs. ISVLSI 2004: 89-98

Mohammad Ibrahim, Earl E. Swartzlander Jr.: Guest Editorial. VLSI Signal Processing 33(1-2): 5 (2003)

Ayman M. El-Khashab, Earl E. Swartzlander Jr.: An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform. ASAP 2003: 378-388

Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.: Quadruple Time Redundancy Adders. DFT 2003: 250-256

Jaeki Yoo, Edward Lee, Earl E. Swartzlander Jr.: A self-testing method for the pipelined A/D converter. ISCAS (1) 2003: 109-112

Sungwook Yu, Earl E. Swartzlander Jr.: A scaled DCT architecture with the CORDIC algorithm. IEEE Transactions on Signal Processing 50(1): 160-167 (2002)

Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr.: A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells. VLSI Signal Processing 31(2): 77-89 (2002)

Chang Yong Kang, Earl E. Swartzlander Jr.: An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis. ASAP 2002: 111-119

Steven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander Jr., Barbara A. Randall: Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS. ASAP 2002: 335-343

Sungwook Yu, Earl E. Swartzlander Jr.: DCT Implementation with Distributed Arithmetic. IEEE Trans. Computers 50(9): 985-991 (2001)

Sungwook Yu, Earl E. Swartzlander Jr.: A pipelined architecture for the multidimensional DFT. IEEE Transactions on Signal Processing 49(9): 2096-2102 (2001)

K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte: Analysis of Column Compression Multipliers. IEEE Symposium on Computer Arithmetic 2001: 33-39

Tat Ngai, Earl E. Swartzlander Jr., Chen He: Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic. DFT 2001: 78-83

Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka: A fast hybrid carry-lookahead/carry-select adder design. ACM Great Lakes Symposium on VLSI 2001: 149-152

Michael J. Schulte, Earl E. Swartzlander Jr.: A Family of Variable-Precision Interval Arithmetic Processors. IEEE Trans. Computers 49(5): 387-397 (2000)

W. Lynn Gallagher, Earl E. Swartzlander Jr.: Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR. IEEE Trans. Computers 49(6): 588-595 (2000)

Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander Jr.: A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms. IEEE Trans. Computers 49(12): 1297-1309 (2000)

Jae-Hyuck Kwak, Jae Hun Choi, Earl E. Swartzlander Jr.: High-Speed CORDIC Based on an Overlapped Architecture and a Novel sigma-Prediction Method. VLSI Signal Processing 25(2): 167-177 (2000)

Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka: A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors. ASAP 2000: 235-

Jae-Hyuck Kwak, Earl E. Swartzlander Jr., Vincenzo Piuri: Fault-Tolerant High-Performance Cordic Processors. DFT 2000: 164-172

Francescomaria Marino, Earl E. Swartzlander Jr.: Parallel Implementation of Multidimensional Transforms without Interprocessor Communication. IEEE Trans. Computers 48(9): 951-961 (1999)

W. Lynn Gallagher, Earl E. Swartzlander Jr.: Power Consumption in Fast Dividers Using Time Shared TMR. DFT 1999: 256-264

Vincenzo Piuri, Earl E. Swartzlander Jr.: Time-Shared Modular Redundancy for Fault-Tolerant FFT Processors. DFT 1999: 265-273

Jae Hun Choi, Jae-Hyuck Kwak, Earl E. Swartzlander Jr.: High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection. ICCD 1999: 68-72

Gwangwoo Choe, Earl E. Swartzlander Jr.: Bipolar merged arithmetic for wavelet architectures. ISCAS (3) 1999: 462-465

Earl E. Swartzlander Jr.: Calculators. IEEE Annals of the History of Computing 20(1): 67-76 (1998)

Earl E. Swartzlander Jr.: Calculators. IEEE Annals of the History of Computing 20(3): 72-73 (1998)

Earl E. Swartzlander Jr.: VLSI, MCM, and WSI: A Design Comparison. IEEE Design & Test of Computers 15(3): 28-34 (1998)

Mary Jane Irwin, Sun-Yuan Kung, Earl E. Swartzlander Jr.: Editorial Message. VLSI Signal Processing 18(1): 7-8 (1998)

W. Lynn Gallagher, Earl E. Swartzlander Jr.: Error-Correcting Goldschmidt Dividers Using Time Shared TMR. DFT 1998: 224-232

Gwangwoo Choe, Earl E. Swartzlander Jr.: Merged Arithmetic for Computing Wavelet Transforms. Great Lakes Symposium on VLSI 1998: 196-201

Moises E. Robinson, Earl E. Swartzlander Jr.: A reduction scheme to optimize the Wallace multiplier. ICCD 1998: 122-127

Earl E. Swartzlander Jr.: Calculators. IEEE Annals of the History of Computing 19(1): 74-75 (1997)

Shaoyun Wang, Vincenzo Piuri, Earl E. Swartzlander Jr.: Hybrid CORDIC Algorithms. IEEE Trans. Computers 46(11): 1202-1207 (1997)

Earl E. Swartzlander Jr.: High-Speed Computer Arithmetic. The Computer Science and Engineering Handbook 1997: 462-481

Thomas K. Callaway, Earl E. Swartzlander Jr.: Power-Delay Characteristics of CMOS Multipliers. IEEE Symposium on Computer Arithmetic 1997: 26-

Hercule Kwan, Edward J. Powers, Earl E. Swartzlander Jr.: Realization of a nonlinear digital filter on a DSP array processor. ASAP 1997: 24-33

W. Lynn Gallagher, Earl E. Swartzlander Jr.: Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMR. DFT 1997: 243-251

Edwin de Angel, Earl E. Swartzlander Jr.: Survey of low power techniques for ROMs. ISLPED 1997: 7-11

Earl E. Swartzlander Jr.: Calculators. IEEE Annals of the History of Computing 18(3): 70-71 (1996)

Earl E. Swartzlander Jr.: Calculators. IEEE Annals of the History of Computing 18(4): 62-64 (1996)

Michael J. Schulte, Earl E. Swartzlander Jr.: Variable-precision, interval arithmetic coprocessors. Reliable Computing 2(1): 47-62 (1996)

Hercule Kwan, Robert Leonard Nelson Jr., Earl E. Swartzlander Jr.: A new design for a lookahead carry generator. VLSI Signal Processing 14(3): 295-302 (1996)

Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr.: Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT. ASAP 1996: 35-

Earl E. Swartzlander Jr.: Calculators. IEEE Annals of the History of Computing 17(3): 75-77 (1995)

Earl E. Swartzlander Jr.: Calculators. IEEE Annals of the History of Computing 17(4): 4 (1995)

K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.: Parallel reduced area multipliers. VLSI Signal Processing 9(3): 181-191 (1995)

Hercule Kwan, Robert Leonard Nelson Jr., Earl E. Swartzlander Jr.: Cascaded Implementation of an Iterative Inverse--Square--Root Algorithm, with Overflow Lookahead. IEEE Symposium on Computer Arithmetic 1995: 115-

Michael J. Schulte, Earl E. Swartzlander Jr.: Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor. IEEE Symposium on Computer Arithmetic 1995: 222-229

Yuang-Ming Hsu, Earl E. Swartzlander Jr., Vincenzo Piuri: Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural Networks. ASAP 1995: 54-65

Michael J. Schulte, Earl E. Swartzlander Jr.: A Processor for Staggered Interval Arithmetic. ASAP 1995: 104-112

Hyesook Lim, Earl E. Swartzlander Jr.: An efficient systolic array for the discrete cosine transform based on prime-factor decomposition . ICCD 1995: 644-649

Michael J. Schulte, Earl E. Swartzlander Jr.: A coprocessor for accurate and reliable numerical computations. ICCD 1995: 686-

Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.: Time-Redundant Multiple Computation for Fault-Tolerant Digital Neural Networks. ISCAS 1995: 977-980

Shaoyun Wang, Earl E. Swartzlander Jr.: Merged CORDIC Algorithm. ISCAS 1995: 1988-1991

Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.: Fault-Tolerant Neural Architectures: The Use of Rotated Operands. ISCAS 1995: 2201-2204

Michael J. Schulte, J. Omar, Earl E. Swartzlander Jr.: Optimal initial approximations for the Newton-Raphson division algorithm. Computing 53(3-4): 233-242 (1994)

Thomas A. Ziaja, Earl E. Swartzlander Jr.: Boundary scan in board manufacturing. J. Electronic Testing 5(2-3): 263-268 (1994)

Michael J. Schulte, Earl E. Swartzlander Jr.: Hardware Designs for Exactly Rounded Elemantary Functions. IEEE Trans. Computers 43(8): 964-973 (1994)

Robert F. Jones, Earl E. Swartzlander Jr.: Parallel counter implementation. VLSI Signal Processing 7(3): 223-232 (1994)

Ben C. Drerup, Earl E. Swartzlander Jr.: Fast multiplier bit-product matrix reduction using bit-ordering and parity generation. VLSI Signal Processing 7(3): 249-257 (1994)

Earl E. Swartzlander Jr.: Editorial. VLSI Signal Processing 8(1): 5 (1994)

Yuang-Ming Hsu, Earl E. Swartzlander Jr.: Reliability Estimation for Time Redundant Error Correcting Adders and Multipliers. DFT 1994: 159-167

Edwin de Angel, Earl E. Swartzlander Jr., Jacob A. Abraham: A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic. ICCD 1994: 302-305

Earl E. Swartzlander Jr.: Heterogeneous Parallel Computing. ICPADS 1994: 8-9

José Duato, C. T. Howard Ho, Ferng-Ching Lin, Lionel M. Ni, Earl E. Swartzlander Jr.: Is It Possible to Fairly Compare Interconnection Networks?. ICPADS 1994: 16-19

Thomas L. Casavant, Chi-Yuan Chin, Wen-Tsuen Chen, Kang G. Shin, Earl E. Swartzlander Jr., Joseph E. Urban: What Types of Research Papers Should We Be Writing? ICPADS 1994: 22-23

Yuang-Ming Hsu, Earl E. Swartzlander Jr.: Sorting Networks with Built-In Error Correction. ICPADS 1994: 379-385

Mohammad S. Khan, Earl E. Swartzlander Jr.: A Standardized Interface Control Unit for Heterogeneous Digital Signal Processors. ISCAS 1994: 97-100

Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.: Modified Booth algorithm for high radix fixed-point multiplication. IEEE Trans. VLSI Syst. 1(2): 164-167 (1993)

Michael J. Schulte, Earl E. Swartzlander Jr.: Exact rounding of certain elementary functions. IEEE Symposium on Computer Arithmetic 1993: 138-145

Thomas K. Callaway, Earl E. Swartzlander Jr.: Estimating the power consumption of CMOS adders. IEEE Symposium on Computer Arithmetic 1993: 210-216

Yuang-Ming Hsu, Earl E. Swartzlander Jr.: VLSI Concurrent Error Correcting Adders and Multipliers. DFT 1993: 287-294

Rathish Jayabharathi, Thomas Thomas, Earl E. Swartzlander Jr.: A Comparative Evaluation of Adders Based on Performance and Testability. ICCD 1993: 314-317

Ishaq H. Unwala, Earl E. Swartzlander Jr.: Superpipelined Adder Designs. ISCAS 1993: 1841-1844

Earl E. Swartzlander Jr., Mary Jane Irwin, Graham A. Jullien (Eds.): 11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings. IEEE Computer Society/ 1993, isbn 0-8186-3862-1

W. Kent Fuchs, Earl E. Swartzlander Jr.: Wafer-Scale Integration: Architectures and Algorithms - Guest Editors' Introduction. IEEE Computer 25(4): 6-8 (1992)

Thomas Lynch, Earl E. Swartzlander Jr.: A Spanning Tree Carry Lookahead Adder. IEEE Trans. Computers 41(8): 931-939 (1992)

Earl E. Swartzlander Jr., Vijay K. Jain, Hiroomi Hikawa: A radix-8 wafer scale FFT processor. VLSI Signal Processing 4(2-3): 165-176 (1992)

Vijay K. Jain, Gibert E. Perez, Earl E. Swartzlander Jr.: Arithmetic Error Analysis of a new Reciprocal Cell. ICCD 1992: 106-109

Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.: Modified Booth Algorihtm for High Radix Multiplication. ICCD 1992: 118-121

Thomas K. Callaway, Earl E. Swartzlander Jr.: Implementation of Parallel Processors with Wafer Scale Integration. IPPS 1992: 268-274

Mayur Mehta, Vijay Parmar, Earl E. Swartzlander Jr.: High-speed multiplier design using multi-input counter and compressor circuits. IEEE Symposium on Computer Arithmetic 1991: 43-50

Dapeng Zhang, Graham A. Jullien, William C. Miller, Earl E. Swartzlander Jr.: Arithmetic for digital neural networks. IEEE Symposium on Computer Arithmetic 1991: 58-63

Thomas Lynch, Earl E. Swartzlander Jr.: The redundant cell adder. IEEE Symposium on Computer Arithmetic 1991: 165-170

Earl E. Swartzlander Jr.: Editorial. VLSI Signal Processing 2(1): 5 (1990)

Earl E. Swartzlander Jr.: Generic signal processor implementation with VHSIC. VLSI Signal Processing 2(2): 111-116 (1990)

Earl E. Swartzlander Jr.: Editorial. VLSI Signal Processing 1(1): 5 (1989)

Earl E. Swartzlander Jr.: Editorial. VLSI Signal Processing 1(2): 91 (1989)

Earl E. Swartzlander Jr.: Editorial. VLSI Signal Processing 1(3): 167 (1989)

Stephen F. Lundstrom, Earl E. Swartzlander Jr.: Foreword: Advances in Distributed Computing Systems. IEEE Trans. Software Eng. 11(10): 1092-1096 (1985)

Earl E. Swartzlander Jr., John A. Eldon: Arithmetic for high speed FFT implementation. IEEE Symposium on Computer Arithmetic 1985: 223-230

Earl E. Swartzlander Jr., John A. Eldon, De D. Hsu: VLSI Testing: A Decade of Experience. COMPCON 1985: 392-396

Earl E. Swartzlander Jr., D. V. Satish Chandra, H. Troy Nagle Jr., Scott A. Starks: Sign/Logarithm Arithmetic for FFT Implementation. IEEE Trans. Computers 32(6): 526-534 (1983)

Earl E. Swartzlander Jr., Barry K. Gilbert: Supersystems: Technology and Architecture. IEEE Trans. Computers 31(5): 399-409 (1982)

Earl E. Swartzlander Jr., Barry K. Gilbert: Arithmetic for Ultra-High-Speed Tomography. IEEE Trans. Computers 29(5): 341-353 (1980)

Earl E. Swartzlander Jr.: Merged Arithmetic. IEEE Trans. Computers 29(10): 946-950 (1980)

Earl E. Swartzlander Jr., Douglas J. Heath: A Routing Algorithm for Signal Processing Networks. IEEE Trans. Computers 28(8): 567-572 (1979)

Earl E. Swartzlander Jr.: Comment on ``The Focus Number System''. IEEE Trans. Computers 28(9): 693 (1979)

Earl E. Swartzlander Jr.: Microprogrammed Control for Specialized Processors. IEEE Trans. Computers 28(12): 930-934 (1979)

Earl E. Swartzlander Jr., Barry K. Gilbert, Irving S. Reed: Inner Product Computers. IEEE Trans. Computers 27(1): 21-31 (1978)

Earl E. Swartzlander Jr.: Merged arithmetic for signal processing. IEEE Symposium on Computer Arithmetic 1978: 239-244

Earl E. Swartzlander Jr., Aristides G. Alexopoulos: The Sign/Logarithm Number System. IEEE Trans. Computers 24(12): 1238-1242 (1975)