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Akira Tada
2000 – 2009
- 2008
[j3]Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi: Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation. JCP 3(5): 34-40 (2008)- 2007
- [j2]Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi, Shigeto Maegawa: Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation. IEICE Transactions 90-C(4): 666-674 (2007)
- [j1]Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi: Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM. IEICE Transactions 90-A(12): 2691-2694 (2007)
- [c4]Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi: Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM. VLSI Design 2007: 609-614
- 2006
- [c3]Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maegawa: High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI. PATMOS 2006: 393-402
- 2004
- [c2]Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada: Leakage power reduction for clock gating scheme on PD-SOI. ISCAS (2) 2004: 613-616
- [c1]Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada: A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI. PATMOS 2004: 423-432
Coauthor Index
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last updated on 2012-12-02 21:48 CET by the dblp team