Eiichi Takahashi

Hirotaka Nosato, Yukari Ishida, Tatsumi Furuya, Eiichi Takahashi, Masahiro Murakawa, Isamu Kajitani, Tetsuya Higuchi: World-Wide Accessible LDPC Encoder/Decoder Generator Using Web-Based GUI and API. CIMCA/IAWTIC/ISE 2008: 627-632

Tatsuya Susa, Masahiro Murakawa, Eiichi Takahashi, Tatsumi Furuya, Tetsuya Higuchi: Post-Fabrication Clock-Timing Adjustment for Digital LSIs Ensuring Operational Timing Margins. HIS 2008: 907-910

Yukari Ishida, Hirotaka Nosato, Eiichi Takahashi, Masahiro Murakawa, Isamu Kajitani, Tatsumi Furuya, Tetsuya Higuchi: Proposal for LDPC Code Design System Using Multi-Objective Optimization and FPGA-Based Emulation. ICES 2008: 237-248

Tetsuaki Matsunawa, Hirokazu Nosato, Hidenori Sakanashi, Masahiro Murakawa, Eiichi Takahashi, Tsuneo Terasawa, Toshihiko Tanaka, Osamu Suga, Tetsuya Higuchi: Adaptive Optical Proximity Correction Using an Optimization Method. CIT 2007: 853-860

Yosuke Iijima, Masahiro Murakawa, Yuji Kasai, Eiichi Takahashi, Tetsuya Higuchi: Proposal of transmission line modeling using multi-objective optimization techniques. IEEE Congress on Evolutionary Computation 2007: 2094-2100

Yuji Kasai, Kiyoshi Miyashita, Hidenori Sakanashi, Eiichi Takahashi, Masaya Iwata, Masahiro Murakawa, Kiyoshi Watanabe, Yukihiro Ueda, Kaoru Takasuka, Tetsuya Higuchi: An Image Rejection Mixer with AI-Based Improved Performance for WCDMA Applications. IEICE Transactions 89-C(6): 717-724 (2006)

Yuji Kasai, Eiichi Takahashi, Masaya Iwata, Yosuke Iijima, Hidenori Sakanashi, Masahiro Murakawa, Tetsuya Higuchi: Adaptive Waveform Control in a Data Transceiver for Multi-speed IEEE1394 and USB Communication. ICES 2005: 198-204

Masahiro Murakawa, Eiichi Takahashi, Tatsuya Susa, Tetsuya Higuchi: Post-fabrication clock timing adjustment for digital LSIs with genetic algorithms ensuring timing margins. SMC (4) 2004: 3670-3674

Eiichi Takahashi, Masahiro Murakawa, Yuji Kasai, Tetsuya Higuchi: Power Dissipation Reductions with Genetic Algorithms. Evolvable Hardware 2003: 111-116

Neil Marston, Eiichi Takahashi, Masahiro Murakawa, Yuji Kasai, Tetsuya Higuchi, Toshio Adachi, Kaoru Takasuka: An Evolutionary Approach to GHz Digital Systems. Evolvable Hardware 2000: 125-132

Tetsuya Higuchi, Masaya Iwata, Didier Keymeulen, Hidenori Sakanashi, Masahiro Murakawa, Isamu Kajitani, Eiichi Takahashi, Kenji Toda, Mehrdad Salami, Nobuki Kajihara, Nobuyuki Otsu: Real-world applications of analog and digital evolvable hardware . IEEE Trans. Evolutionary Computation 3(3): 220-235 (1999)

Prashant R. Chandra, Allan Fisher, Corey Kosak, T. S. Eugene Ng, Peter Steenkiste, Eiichi Takahashi, Hui Zhang: Darwin: Customizable Resource Management for Value-Added Network Services. ICNP 1998: 177-188

Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi: CODA-R: a reconfigurable testbed for real-time parallel computation. RTCSA 1997: 252-259

Heejo Lee, Kenji Toda, Jong Kim, Kenji Nishida, Eiichi Takahashi, Yoshinori Yamaguchi: Performance comparison of real-time architectures using simulation. RTCSA 1995: 150-

Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi: The Execution Model and the Architecture for Real-Time Parallel Systems. IFIP Congress (1) 1994: 177-182

Shigeru Kusakabe, Eiichi Takahashi, Rin-ichiro Taniguchi, Makoto Amamiya: Dataflow-Based Lenient Implementation of a Functional Language, Valid, on Conventional Multi-processors. IFIP PACT 1994: 279-288

Shigeru Kusakabe, Eiichi Takahashi, Rin-ichiro Taniguchi, Makoto Amamiya: A Dataflow-Based Massively Parallel Programming Language and Its Implementation. PARLE 1994: 761-764

Kenji Toda, Kenji Nishida, Eiichi Takahashi, Yoshinori Yamaguchi: A Priority Forwarding Router Chip for Real-Time Interconnection Networks. RTSS 1994: 63-73