Kesava R. Talupuru

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	2011
c2		Kesava R. Talupuru, Sanjai Athi: Achieving Glitch-Free Clock Domain Crossing Signals Using Formal Verification, Static Timing Analysis, and Sequential Equivalence Checking. MTV 2011: 5-9
	2008
c1		Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang: Simulation Acceleration with HW Re-Compilation Avoidance. VLSI Design 2008: 487-491
	2005
j1		Zhihong Zeng, Kesava R. Talupuru, Maciej J. Ciesielski: Functional test generation based on word-level SAT. Journal of Systems Architecture 51(8): 488-511 (2005)

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Last update Mon May 20 11:21:48 2013 CET by the DBLP Team —

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