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 | 2000 | |
|---|---|---|
| c18 |      | Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru: A method for linking process-level variability to system performances. ASP-DAC 2000: 547-552 |
| 1999 | ||
| c17 | | Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru: A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. DAC 1999: 446-451 |
| 1998 | ||
| j4 | | Vasily G. Moshnyaga, Naoto Watanabe, Keikichi Tamaru: A memory efficient array architecture for real-time motion estimation. Systems and Computers in Japan 29(9): 13-20 (1998) |
| j3 | | Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru: Model-adaptable MOSFET parameter-extraction method using an intermediate model. IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 400-405 (1998) |
| c16 | | Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru: Proposal of a timing model for CMOS logic gates driving a CRC load. ICCAD 1998: 537-544 |
| c15 | | Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru: A power optimization method considering glitch reduction by gate sizing. ISLPED 1998: 221-226 |
| 1997 | ||
| c14 | | Kazutoshi Kobayashi, Masayoshi Kinoshita, M. Takeuchi, Hidetoshi Onodera, Keikichi Tamaru: A functional memory type parallel processor for vector quantization. ASP-DAC 1997: 665-666 |
| c13 | | Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru: A current mode cyclic A/D converter with a 0.8 μm CMOS process. ASP-DAC 1997: 683-684 |
| c12 | | Vasily G. Moshnyaga, Keikichi Tamaru: A Memory Efficient Array Architecture for Real-Time Motion Estimation. IPPS 1997: 28-32 |
| 1996 | ||
| c11 | | Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru: Timing and Power Optimization by Gate Sizing Considering False Paths. Great Lakes Symposium on VLSI 1996: 154- |
| 1995 | ||
| j2 | | Vasily G. Moshnyaga, Yutaka Mori, Keikichi Tamaru: Register-Transfer Module Selection for Sub-Micron ASIC Design. IEICE Transactions 78-D(3): 252-255 (1995) |
| j1 | | Farhad Fuad Islam, Keikichi Tamaru: High speed merged array multiplication. VLSI Signal Processing 10(1): 41-52 (1995) |
| c10 | | Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru: A model-adaptable MOSFET parameter extraction system. ASP-DAC 1995 |
| c9 | | Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru: A scheduling algorithm for synthesis of bus-partitioned architectures. ASP-DAC 1995 |
| c8 | | Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru: An iterative gate sizing approach with accurate delay evaluation. ICCAD 1995: 422-427 |
| c7 |  | Kuei-Ming Lu, Keikichi Tamaru: A New Algorithm for Sorting Problem with Reformed CAM. ISCAS 1995: 1045-1048 |
| c6 | | Vasily G. Moshnyaga, Keikichi Tamaru: A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers. ISCAS 1995: 1560-1563 |
| 1993 | ||
| c5 | | Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru: Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. ICCAD 1993: 100-103 |
| c4 | | Farhad Fuad Islam, Keikichi Tamaru: An Architecture for Intermediate Area-time Complexity Multiplier. ISCAS 1993: 1825-1828 |
| 1992 | ||
| c3 | | Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura: Design of data-path module generators from algorithmic representations. Synthesis for Control Dominated Circuits 1992: 183-192 |
| 1991 | ||
| c2 | | Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru: Branch-and-Bound Placement for Building Block Layout. DAC 1991: 433-439 |
| 1990 | ||
| c1 | | M. Ohmura, Hiroto Yasuura, Keikichi Tamaru: Extraction of Functional Information from Combinatorial Circuits. ICCAD 1990: 176-179 |
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