Sheldon X.-D. Tan

Zhigang Hao, Sheldon X.-D. Tan, Guoyong Shi: Statistical full-chip total power estimation considering spatially correlated process variations. Integration 46(1): 80-88 (2013)

Hai Wang, Sheldon X.-D. Tan, Duo Li, Ashish Gupta, Yuan Yuan: Composable thermal modeling and simulation for architecture-level thermal designs of multicore microprocessors. ACM Trans. Design Autom. Electr. Syst. 18(2): 28 (2013)

Zhigang Hao, Guoyong Shi, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle: Symbolic Moment Computation for Statistical Analysis of Large Interconnect Networks. IEEE Trans. VLSI Syst. 21(5): 944-957 (2013)

Zao Liu, Sheldon X.-D. Tan, Hai Wang, Sahana Swarup, Ashish Gupta: Compact nonlinear thermal modeling of packaged integrated systems. ASP-DAC 2013: 157-162

Zao Liu, Tailong Xu, Sheldon X.-D. Tan, Hai Wang: Dynamic thermal management for multi-core microprocessors considering transient thermal effects. ASP-DAC 2013: 473-478

Xuexin Liu, Adolfo Adair Palma-Rodriguez, Santiago Rodriguez-Chavez, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle, Yici Cai: Performance bound and yield analysis for analog circuits under process variations. ASP-DAC 2013: 761-766

Hai Wang, Sheldon X.-D. Tan, Sahana Swarup, Xuexin Liu: A power-driven thermal sensor placement algorithm for dynamic thermal management. DATE 2013: 1215-1220

Zuying Luo, Guoxing Zhao, Joseph A. Gordon, Sheldon X.-D. Tan: Localized relaxation theory of circuits and its applications in electro-thermal analyses. SCIENCE CHINA Information Sciences 55(4): 938-950 (2012)

Hai Wang, Hao Yu, Sheldon X.-D. Tan: Fast timing analysis of clock networks considering environmental uncertainty. Integration 45(4): 376-387 (2012)

Hai Wang, Sheldon X.-D. Tan, Ryan Rakib: Compact Modeling of Interconnect Circuits over Wide Frequency Band by Adaptive Complex-Valued Sampling Method. ACM Trans. Design Autom. Electr. Syst. 17(1): 5 (2012)

Fang Gong, Xuexin Liu, Hao Yu, Sheldon X.-D. Tan, Junyan Ren, Lei He: A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials. ACM Trans. Design Autom. Electr. Syst. 17(1): 10 (2012)

Ruijing Shen, Sheldon X.-D. Tan, Hai Wang, Jinjun Xiong: Fast Statistical Full-Chip Leakage Analysis for Nanometer VLSI Systems. ACM Trans. Design Autom. Electr. Syst. 17(4): 51 (2012)

Thom Jefferson A. Eguia, Sheldon X.-D. Tan, Ruijing Shen, Duo Li, Eduardo H. Pacheco, Murli Tirumala, Lingli Wang: General Parameterized Thermal Modeling for High-Performance Microprocessor Design. IEEE Trans. VLSI Syst. 20(2): 211-224 (2012)

Boyuan Yan, Sheldon X.-D. Tan, Lingfei Zhou, Jie Chen, Ruijing Shen: Decentralized and Passive Model Order Reduction of Linear Networks With Massive Ports. IEEE Trans. VLSI Syst. 20(5): 865-877 (2012)

Xuexin Liu, Sheldon X.-D. Tan, Zhigang Hao, Guoyong Shi: Time-domain performance bound analysis of analog circuits considering process variations. ASP-DAC 2012: 535-540

Hai Wang, Sheldon X.-D. Tan, Xuexin Liu, Ashish Gupta: Runtime power estimator calibration for high-performance microprocessors. DATE 2012: 352-357

Xuexin Liu, Sheldon X.-D. Tan, Hai Wang: Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach. DATE 2012: 852-857

Xuexin Liu, Sheldon X.-D. Tan, Hai Wang, Hao Yu: A GPU-accelerated envelope-following method for switching power converter simulation. DATE 2012: 1349-1354

Xuexin Liu, Zao Liu, Sheldon X.-D. Tan, Joseph A. Gordon: Full-chip thermal analysis of 3D ICs with liquid cooling by GPU-accelerated GMRES method. ISQED 2012: 123-128

Ruijing Shen, Sheldon X.-D. Tan, Xuexin Liu: A new voltage binning technique for yield improvement based on graph theory. ISQED 2012: 243-248

Carlos Sánchez-López, Francisco V. Fernández, Esteban Tlelo-Cuautle, Sheldon X.-D. Tan: Pathological Element-Based Active Device Models and Their Application to Symbolic Analysis. IEEE Trans. on Circuits and Systems 58-I(6): 1382-1395 (2011)

Xuexin Liu, Hao Yu, Jacob Relles, Sheldon X.-D. Tan: A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms. ASP-DAC 2011: 13-18

Zhigang Hao, Sheldon X.-D. Tan, Ruijing Shen, Guoyong Shi: Performance bound analysis of analog circuits considering process variations. DAC 2011: 310-315

Zao Liu, Sheldon X.-D. Tan, Hai Wang, Rafael Quintanilla, Ashish Gupta: Compact thermal modeling for package design with practical power maps. IGCC 2011: 1-5

Hai Wang, Sheldon X.-D. Tan, Guangdeng Liao, Rafael Quintanilla, Ashish Gupta: Full-chip runtime error-tolerant thermal estimation and prediction for practical thermal management. ICCAD 2011: 716-723

Zhigang Hao, Sheldon X.-D. Tan, Guoyong Shi: An efficient statistical chip-level total power estimation method considering process variations with spatial correlation. ISQED 2011: 671-676

Zhigang Hao, Ruijing Shen, Sheldon X.-D. Tan, Bao Liu, Guoyong Shi, Yici Cai: Statistical full-chip dynamic power estimation considering spatial correlations. ISQED 2011: 677-682

Ruijing Shen, Sheldon X.-D. Tan, Ning Mi, Yici Cai: Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. Integration 43(1): 156-165 (2010)

Duo Li, Sheldon X.-D. Tan: Statistical analysis of large on-chip power grid networks by variational reduction scheme. Integration 43(2): 167-175 (2010)

Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fan: Passive Rational Interpolation-Based Reduction via Carathéodory Extension for General Systems. IEEE Trans. on Circuits and Systems 57-II(9): 750-755 (2010)

Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala: Parameterized architecture-level dynamic thermal models for multicore microprocessors. ACM Trans. Design Autom. Electr. Syst. 15(2) (2010)

Hao Yu, Chunta Chu, Yiyu Shi, David Smart, Lei He, Sheldon X.-D. Tan: Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling. IEEE Trans. VLSI Syst. 18(10): 1399-1411 (2010)

Ruijing Shen, Sheldon X.-D. Tan, Jian Cui, Wenjian Yu, Yici Cai, Gengsheng Chen: Variational Capacitance Extraction and Modeling Based on Orthogonal Polynomial Method. IEEE Trans. VLSI Syst. 18(11): 1556-1566 (2010)

Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Yici Cai: Efficient model reduction of interconnects via double gramians approximation. ASP-DAC 2010: 25-30

Hai Wang, Sheldon X.-D. Tan, Gengsheng Chen: Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method. ASP-DAC 2010: 31-36

Hao Yu, Xuexin Liu, Hai Wang, Sheldon X.-D. Tan: A fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel. ASP-DAC 2010: 211-216

Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai: Efficient power grid integrity analysis using on-the-fly error check and reduction. ASP-DAC 2010: 763-768

Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong: A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation. DAC 2010: 481-486

Xuexin Liu, Hao Yu, Sheldon X.-D. Tan: A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs. DAC 2010: 573-578

Thom Jefferson A. Eguia, Sheldon X.-D. Tan, Ruijing Shen, Eduardo H. Pacheco, Murli Tirumala: General behavioral thermal modeling and characterization for multi-core microprocessor design. DATE 2010: 1136-1141

Kejie Ma, Lingli Wang, Xuegong Zhou, Sheldon X.-D. Tan, Jiarong Tong: General switch box modeling and optimization for FPGA routing architectures. FPT 2010: 320-323

Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong: A linear statistical analysis for full-chip leakage power with spatial correlation. ACM Great Lakes Symposium on VLSI 2010: 227-232

Esteban Tlelo-Cuautle, Elyoenai Martínez-Romero, Carlos Sánchez-López, Sheldon X.-D. Tan: Symbolic behavioral modeling of low voltage amplifiers. CCE 2010: 510-514

Duo Li, Sheldon X.-D. Tan: Fast Analysis of On-Chip Power Grid Circuits by Extended Truncated Balanced Realization Method. IEICE Transactions 92-A(12): 3061-3069 (2009)

Ning Mi, Sheldon X.-D. Tan, Boyuan Yan: Multiple block structure-preserving reduced order modeling of interconnect circuits. Integration 42(2): 158-168 (2009)

Duo Li, Sheldon X.-D. Tan, Lifeng Wu: Hierarchical Krylov subspace based reduction of large interconnects. Integration 42(2): 193-202 (2009)

Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala: Architecture-Level Thermal Characterization for Multicore Microprocessors. IEEE Trans. VLSI Syst. 17(10): 1495-1507 (2009)

Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. ASP-DAC 2009: 161-166

Duo Li, Sheldon X.-D. Tan, Gengsheng Chen, Xuan Zeng: Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method. ASP-DAC 2009: 272-277

Hai Wang, Hao Yu, Sheldon X.-D. Tan: Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling. ASP-DAC 2009: 379-384

Jin Shi, Yici Cai, Wenting Hou, Liwei Ma, Sheldon X.-D. Tan, Pei-Hsin Ho, Xiaoyi Wang: GPU friendly fast Poisson solver for structured power grid network analysis. DAC 2009: 178-183

Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles: An efficient decoupling capacitance optimization using piecewise polynomial models. DATE 2009: 1190-1195

Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. Tan, Thom Jefferson A. Eguia: Decoupling capacitance efficient placement for reducing transient power supply noise. ICCAD 2009: 745-751

Esteban Tlelo-Cuautle, Elyoenai Martínez-Romero, Carlos Sánchez-López, Sheldon X.-D. Tan: Symbolic formulation method for mixed-mode analog circuits using nullors. ICECS 2009: 856-859

Zuying Luo, Jeffrey Fan, Sheldon X.-D. Tan: Localized Statistical 3D Thermal Analysis Considering Electro-Thermal Coupling. ISCAS 2009: 1289-1292

Thom Jefferson A. Eguia, Ning Mi, Sheldon X.-D. Tan: Statistical decoupling capacitance allocation by efficient numerical quadrature method. ISQED 2009: 309-316

Yici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan: Large scale P/G grid transient simulation using hierarchical relaxed approach. Integration 41(1): 153-160 (2008)

Pu Liu, Sheldon X.-D. Tan, Boyuan Yan, Bruce McGaughy: An efficient terminal and model order reduction algorithm. Integration 41(2): 210-218 (2008)

Sheldon X.-D. Tan, Pu Liu, Lin Jiang, Wei Wu, Murli Tirumala: A Fast Architecture-Level Thermal Analysis Method for Runtime Thermal Regulation. J. Low Power Electronics 4(2): 139-148 (2008)

Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 1996-2006 (2008)

Yici Cai, Le Kang, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan: Random Walk Guided Decap Embedding for Power/Ground Network Optimization. IEEE Trans. on Circuits and Systems 55-II(1): 36-40 (2008)

Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation. IEEE Trans. on Circuits and Systems 55-I(7): 2064-2075 (2008)

Boyuan Yan, Sheldon X.-D. Tan, Bruce McGaughy: Second-Order Balanced Truncation for Passive-Order Reduction of RLCK Circuits. IEEE Trans. on Circuits and Systems 55-II(9): 942-946 (2008)

Duo Li, Sheldon X.-D. Tan: Hierarchical Krylov subspace reduced order modeling of large RLC circuits. ASP-DAC 2008: 170-175

Duo Li, Sheldon X.-D. Tan, Murli Tirumala: Architecture-level thermal behavioral characterization for multi-core microprocessors. ASP-DAC 2008: 456-461

Boyuan Yan, Lingfei Zhou, Sheldon X.-D. Tan, Jie Chen, Bruce McGaughy: DeMOR: decentralized model order reduction of linear networks with massive ports. DAC 2008: 409-414

Duo Li, Sheldon X.-D. Tan, Bruce McGaughy: ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis. DATE 2008: 432-437

Jian Cui, Gengsheng Chen, Ruijing Shen, Sheldon X.-D. Tan, Wenjian Yu, Jiarong Tong: Variational capacitance modeling using orthogonal polynomial method. ACM Great Lakes Symposium on VLSI 2008: 23-28

Pu Liu, Sheldon X.-D. Tan, Wei Wu, Murli Tirumala: FEKIS: a fast architecture-level thermal analyzer for online thermal regulation. ACM Great Lakes Symposium on VLSI 2008: 411-416

Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala: Parameterized transient thermal behavioral modeling for chip multiprocessors. ICCAD 2008: 611-617

Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Lifeng Wu: Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method. ICCAD 2008: 744-749

Zuying Luo, Sheldon X.-D. Tan: Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method. ISQED 2008: 867-872

Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Partitioning-based decoupling capacitor budgeting via sequence of linear programming. Integration 40(4): 516-524 (2007)

Jin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong: Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 680-692 (2007)

Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu, Lei He: TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1382-1392 (2007)

Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan: Efficient power modeling and software thermal sensing for runtime temperature monitoring. ACM Trans. Design Autom. Electr. Syst. 12(3) (2007)

Bao Liu, Sheldon X.-D. Tan: Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs. IEEE Trans. VLSI Syst. 15(11): 1284-1287 (2007)

Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy: Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form. ASP-DAC 2007: 355-360

Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang: Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. ASP-DAC 2007: 367-372

Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan: Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach. ASP-DAC 2007: 751-756

Le Kang, Yici Cai, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan, Xiaoyi Wang: Simultaneous Switching Noise Consideration for Power/Ground Network Optimization. CAD/Graphics 2007: 332-337

Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy: SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits. DAC 2007: 158-161

Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Statistical model order reduction for interconnect circuits considering spatial correlations. DATE 2007: 1508-1513

Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong: Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. ICCAD 2007: 48-53

Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan: Voltage drop reduction for on-chip power delivery considering leakage current variations. ICCD 2007: 78-83

Wei Wu, Sheldon X.-D. Tan, Jun Yang, Shih-Lien Lu: Improving the reliability of on-chip data caches under process variations. ICCD 2007: 325-332

Boyuan Yan, Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy: Passive Modeling of Interconnects by Waveform Shaping. ISQED 2007: 356-361

Ning Mi, Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fan, Hao Yu: General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits. ISQED 2007: 633-638

Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu: Time-domain analysis methodology for large-scale RLC circuits and its applications. Science in China Series F: Information Sciences 49(5): 665-680 (2006)

Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He: Wideband passive multiport model order reduction and realization of RLCM circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1496-1509 (2006)

Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2402-2412 (2006)

Pu Liu, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang: Fast Thermal Simulation for Runtime Temperature Tracking and Management. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2882-2893 (2006)

Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong: Efficient early stage resonance estimation techniques for C4 package. ASP-DAC 2006: 826-831

Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan: A systematic method for functional unit power estimation in microprocessors. DAC 2006: 554-557

Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan: Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation. ICCD 2006

Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan: Efficient decoupling capacitor planning via convex programming methods. ISPD 2006: 102-107

Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong: High accurate pattern based precondition method for extremely large power/ground grid analysis. ISPD 2006: 108-113

Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming. ISQED 2006: 272-277

Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu: Compact Reduced Order Modeling for Multiple-Port Interconnects. ISQED 2006: 413-418

Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan: SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. ISQED 2006: 638-643

Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan: A Fast Delay Computation for the Hybrid Structured Clock Network. IEICE Transactions 88-A(7): 1964-1970 (2005)

Sheldon X.-D. Tan: A general hierarchical circuit modeling and simulation algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 418-434 (2005)

Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi: Hierarchical approach to exact symbolic analysis of large analog circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1241-1250 (2005)

Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan: Analysis of buffered hybrid structured clock networks. ASP-DAC 2005: 93-98

Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan: A wideband hierarchical circuit reduction for massively coupled interconnects. ASP-DAC 2005: 111-114

Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He: Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction. ASP-DAC 2005: 224-229

Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan: VLSI on-chip power/ground network optimization considering decap leakage currents. ASP-DAC 2005: 735-738

Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu: Relaxed hierarchical power/ground grid analysis. ASP-DAC 2005: 1090-1093

Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Partitioning-based approach to fast on-chip decap budgeting and minimization. DAC 2005: 170-175

Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan: A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. FCCM 2005: 57-62

Pu Liu, Zhenyu Qi, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang: Fast thermal simulation for architecture level dynamic thermal management. ICCAD 2005: 639-644

Pu Liu, Sheldon X.-D. Tan, Hang Li, Zhenyu Qi, Jun Kong, Bruce McGaughy, Lei He: An efficient method for terminal reduction of interconnect circuits considering delay variations. ICCAD 2005: 821-826

Hang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang: Efficient Thermal Simulation for Run-Time Temperature Tracking and Management. ICCD 2005: 130-136

Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. ISQED 2005: 542-547

Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan: Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits. ISQED 2005: 603-608

Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan: Efficient Simulation of Power/Ground Networks with Package and Vias. PATMOS 2005: 318-328

Sheldon X.-D. Tan, C.-J. Richard Shi: Efficient approximation of symbolic expressions for analog behavioral modeling and analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 907-918 (2004)

Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan: A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. ASP-DAC 2004: 505-510

Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi: Hierarchical approach to exact symbolic analysis of large analog circuits. DAC 2004: 860-863

Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan: Dynamic FPGA routing for just-in-time FPGA compilation. DAC 2004: 954-959

Sheldon X.-D. Tan, Zhenyu Qi, Hang Li: Hierarchical Modeling and Simulation of Large Analog Circuits. DATE 2004: 740-741

Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan: A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. ICCD 2004: 344-349

Junjie Yang, Sheldon X.-D. Tan: Behavioural modelling of analog circuits by dynamic semi-symbolic analysis. ISCAS (5) 2004: 105-108

Junjie Yang, Sheldon X.-D. Tan: An efficient algorithm for transient and distortion analysis of mildly nonlinear analog circuits. ISCAS (5) 2004: 129-132

Weikun Guo, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong: Partial random walk for large linear network analysis. ISCAS (5) 2004: 173-177

Zhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong: Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling. ISQED 2004: 63-68

Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan: Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. PATMOS 2004: 433-441

Sheldon X.-D. Tan, C.-J. Richard Shi: Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis. Integration 34(1-2): 65-86 (2003)

Sheldon X.-D. Tan, C.-J. Richard Shi: Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 277-284 (2003)

Sheldon X.-D. Tan, C.-J. Richard Shi, Jyh-Chwen Lee: Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings. IEEE Trans. on CAD of Integrated Circuits and Systems 22(12): 1678-1684 (2003)

Sheldon X.-D. Tan, C.-J. Richard Shi: Efficient DDD-based term generation algorithm for analog circuit behavioral modeling. ASP-DAC 2003: 789-794

Sheldon X.-D. Tan: A General S-Domain Hierarchical Network Reduction Algorithm. ICCAD 2003: 650-657

Qi-De Qian, Sheldon X.-D. Tan: Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis. ISQED 2003: 125-130

C.-J. Richard Shi, Sheldon X.-D. Tan: Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design. IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 813-827 (2001)

Sheldon X.-D. Tan, C.-J. Richard Shi: Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling. DAC 2001: 550-554

C.-J. Richard Shi, Sheldon X.-D. Tan: Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 1-18 (2000)

Sheldon X.-D. Tan, C.-J. Richard Shi: Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 401-412 (2000)

Xiang-Dong Tan, C.-J. Richard Shi: Symbolic circuit-noise analysis and modeling with determinant decision diagrams. ASP-DAC 2000: 283-288

Xiang-Dong Tan, C.-J. Richard Shi: Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis. ASP-DAC 1999: 1-4

Xiang-Dong Tan, C.-J. Richard Shi, Dragos Lungeanu, Jyh-Chwen Lee, Li-Pen Yuan: Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings. DAC 1999: 78-83

Xiang-Dong Tan, C.-J. Richard Shi: Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams. DATE 1999: 448-453

C.-J. Richard Shi, Xiang-Dong Tan: Symbolic analysis of large analog circuits with determinant decision diagrams. ICCAD 1997: 366-373