| 2013 | ||
|---|---|---|
| j9 | Linjun Fan, Yunxiang Ling, Tao Wang, Xiaomin Zhu, Xiaoyong Tang: Novel clock synchronization algorithm of parametric difference for parallel and distributed simulations. Computer Networks 57(6): 1474-1487 (2013) | |
| 2012 | ||
| j8 | Xiaoyong Tang, Kenli Li, Meikang Qiu, Edwin Hsing-Mean Sha: A hierarchical reliability-driven scheduling algorithm in grid systems. J. Parallel Distrib. Comput. 72(4): 525-535 (2012) | |
| c13 | Kenli Li, Xiaoyong Tang, Qifeng Yin: Energy-Aware Scheduling Algorithm for Task Execution Cycles with Normal Distribution on Heterogeneous Computing Systems. ICPP 2012: 40-47 | |
| 2011 | ||
| j7 | Kenli Li, Tianfang Tan, Xiaoyong Tang, Feng Wang: Parallelization methods for implementation of discharge simulation along resin insulator surfaces. Computers & Electrical Engineering 37(1): 30-40 (2011) | |
| j6 | Xiaoyong Tang, Kenli Li, Guiping Liao, Kui Fang, Fan Wu: A stochastic scheduling algorithm for precedence constrained tasks on Grid. Future Generation Comp. Syst. 27(8): 1083-1091 (2011) | |
| j5 | Xiaoyong Tang, Kenli Li, Zeng Zeng, Bharadwaj Veeravalli: A Novel Security-Driven Scheduling Algorithm for Precedence-Constrained Tasks in Heterogeneous Distributed Systems. IEEE Trans. Computers 60(7): 1017-1029 (2011) | |
| 2010 | ||
| j4 | Xiaoyong Tang, Kenli Li, Guiping Liao, Renfa Li: List scheduling with duplication for heterogeneous computing systems. J. Parallel Distrib. Comput. 70(4): 323-329 (2010) | |
| j3 | Xiaoyong Tang, Kenli Li, Renfa Li, Bharadwaj Veeravalli: Reliability-aware scheduling strategy for heterogeneous distributed computing systems. J. Parallel Distrib. Comput. 70(9): 941-952 (2010) | |
| c12 | Xiaochun Li, Tiejun Zhou, Xiaoyong Tang, Xiangwen Cai: Identification of coding and non-coding sequences in a complete genome using local Hölder exponent formalism and Multi-affinity analysis. BIC-TA 2010: 775-782 | |
| c11 | Xiaoyong Tang, Kenli Li, Fan Wu: Approximation for preemptive scheduling stochastic jobs on identical parallel machines. BIC-TA 2010: 1287-1290 | |
| 2007 | ||
| j2 | Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee: An Overview of a Compiler for Mapping Software Binaries to Hardware. IEEE Trans. VLSI Syst. 15(11): 1177-1190 (2007) | |
| 2006 | ||
| c10 | Chunling Zhu, Xiaoyong Tang, Kenli Li, Xiao Han, Xilu Zhu, Xuesheng Qi: Integrating Trust into Grid Economic Model Scheduling Algorithm. OTM Conferences (2) 2006: 1263-1272 | |
| c9 | Xiaoyong Tang, Kenli Li, Degui Xiao, Jing Yang, Min Liu, Yunchuan Qin: A Dynamic Communication Contention Awareness List Scheduling Algorithm for Arbitrary Heterogeneous System. OTM Conferences (2) 2006: 1315-1324 | |
| 2005 | ||
| j1 | Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee: High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits. J. Low Power Electronics 1(3): 259-272 (2005) | |
| c8 | Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee: Leakage power optimization with dual-Vth library in high-level synthesis. DAC 2005: 202-207 | |
| c7 | Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee: Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation. VLSI Design 2005: 267-273 | |
| 2004 | ||
| c6 | Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee: Automatic translation of software binaries onto FPGAs. DAC 2004: 389-394 | |
| c5 | David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee: Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs. FCCM 2004: 37-46 | |
| c4 | Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee: High level area, delay and power estimation for FPGAs. FPGA 2004: 249 | |
| c3 | Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee: Macro-models for high level area and power estimation on FPGAs. ACM Great Lakes Symposium on VLSI 2004: 162-165 | |
| c2 | David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee: Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs. ACM Great Lakes Symposium on VLSI 2004: 397-400 | |
| 2002 | ||
| c1 | Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee: PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. CASES 2002: 188-197 | |
Colors in the list of coauthors
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