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Kazuya Tanigawa
2010 – today
- 2012
[j1]Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro: A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks. IEICE Transactions 95-D(2): 324-334 (2012)- 2011
- [c8]Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro: EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture. ReConFig 2011: 448-454
- 2010
- [c7]Kazuya Tanigawa, Ken'ichi Umeda, Tetsuo Hironaka: Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor. ARC 2010: 388-393
2000 – 2009
- 2008
- [c6]Kazuya Tanigawa, Tetsuya Zuyama, Takuro Uchida, Tetsuo Hironaka: Exploring compact design on high throughput coarse grained reconfigurable architectures. FPL 2008: 543-546
- [c5]Kazuya Tanigawa, Tetsuo Hironaka: Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation. FPT 2008: 273-276
- 2006
- [c4]Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa: Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS 2006: 1297-1300
- 2005
- [c3]T. Saito, M. Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, K. Aoyama, Tetsushi Koide, Hans Jürgen Mattausch: Design of superscalar processor with multi-bank register file. ISCAS (4) 2005: 3507-3510
- 2003
- [c2]Kazuya Tanigawa, Takashi Kawasaki, Tetsuo Hironaka: A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism. FPT 2003: 311-314
- 2002
- [c1]Kazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida: A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model. FPL 2002: 434-443
Coauthor Index
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last updated on 2012-12-02 21:54 CET by the dblp team