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Serdar Tasiran
2010 – today
- 2013
[e2]Shaz Qadeer, Serdar Tasiran (Eds.): Runtime Verification, Third International Conference, RV 2012, Istanbul, Turkey, September 25-28, 2012, Revised Selected Papers. Lecture Notes in Computer Science 7687, Springer 2013, ISBN 978-3-642-35631-5- 2012
- [j14]Serdar Tasiran, M. Erkan Keremoglu, Kivanç Muslu: Location pairs: a test coverage metric for shared-memory concurrent programs. Empirical Software Engineering 17(3): 129-165 (2012)
- [j13]Shaz Qadeer, Serdar Tasiran: Runtime verification of concurrency-specific correctness criteria. STTT 14(3): 291-305 (2012)
- 2010
- [j12]Tayfun Elmas, Shaz Qadeer, Serdar Tasiran: Goldilocks: a race-aware Java runtime. Commun. ACM 53(11): 85-92 (2010)
- [j11]
- [j10]Alp Arslan Bayrakci, Alper Demir, Serdar Tasiran: Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 29(9): 1328-1341 (2010)
- [c23]Ali Sezgin, Serdar Tasiran, Kivanç Muslu, Shaz Qadeer: Run-Time Verification of Optimistic Concurrency. RV 2010: 384-398
- [c22]Tayfun Elmas, Shaz Qadeer, Ali Sezgin, Omer Subasi, Serdar Tasiran: Simplifying Linearizability Proofs with Reduction and Abstraction. TACAS 2010: 296-311
- [c21]
2000 – 2009
- 2009
- [c20]Tayfun Elmas, Ali Sezgin, Serdar Tasiran, Shaz Qadeer: An annotation assistant for interactive debugging of programs with common synchronization idioms. PADTAD 2009
- [c19]
- 2008
- [j9]Soner Yaldiz, Alper Demir, Serdar Tasiran: Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1264-1277 (2008)
- [j8]Nesra Yannier, Cagatay Basdogan, Serdar Tasiran, Omer Lutfi Sen: Using Haptics to Convey Cause-and-Effect Relations in Climate Visualization. IEEE T. Haptics 1(2): 130-141 (2008)
- [i1]Alp Arslan Bayrakci, Alper Demir, Serdar Tasiran: Fast Monte Carlo Estimation of Timing Yield: Importance Sampling with Stochastic Logical Effort (ISLE). CoRR abs/0805.2627 (2008)
- 2007
- [c18]Tayfun Elmas, Shaz Qadeer, Serdar Tasiran: Goldilocks: a race and transaction-aware java runtime. PLDI 2007: 245-255
- [c17]
- [e1]Oleg Sokolsky, Serdar Tasiran (Eds.): Runtime Verification, 7th International Workshop, RV 2007, Vancouver, Canada, March 13, 2007, Revised Selected Papers. Lecture Notes in Computer Science 4839, Springer 2007, ISBN 978-3-540-77394-8
- 2006
- [j7]Tayfun Elmas, Serdar Tasiran: VyrdMC: Driving Runtime Refinement Checking with Model Checkers. Electr. Notes Theor. Comput. Sci. 144(4): 41-56 (2006)
- [c16]Tayfun Elmas, Shaz Qadeer, Serdar Tasiran: Goldilocks: Efficiently Computing the Happens-Before Relation Using Locksets. FATES/RV 2006: 193-208
- [c15]M. Erkan Keremoglu, Serdar Tasiran, Tayfun Elmas: A classification of concurrency bugs in java benchmarks by developer intent. PADTAD 2006: 23-26
- 2005
- [j6]Serdar Tasiran, Shaz Qadeer: Runtime Refinement Checking of Concurrent Data Structures. Electr. Notes Theor. Comput. Sci. 113: 163-179 (2005)
- [c14]Soner Yaldiz, Alper Demir, Serdar Tasiran, Paolo Ienne, Yusuf Leblebici: Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. ESTImedia 2005: 135-140
- [c13]Serdar Tasiran, Tayfun Elmas, Guven Bolukbasi, M. Erkan Keremoglu: A Novel Test Coverage Metric for Concurrently-Accessed Software Components. FATES 2005: 62-71
- [c12]Tayfun Elmas, Serdar Tasiran, Shaz Qadeer: VYRD: verifYing concurrent programs by runtime refinement-violation detection. PLDI 2005: 27-37
- 2004
- [j5]Serdar Tasiran, Yuan Yu, Brannon Batson: Linking Simulation with Formal Verification at a Higher Level. IEEE Design & Test of Computers 21(6): 472-482 (2004)
- 2003
- [j4]Rajeev Joshi, Leslie Lamport, John Matthews, Serdar Tasiran, Mark R. Tuttle, Yuan Yu: Checking Cache-Coherence Protocols with TLA+. Formal Methods in System Design 22(2): 125-131 (2003)
- [j3]Tamara Munzner, François Guimbretière, Serdar Tasiran, Li Zhang, Yunhong Zhou: TreeJuxtaposer: scalable tree comparison using Focus+Context with guaranteed visibility. ACM Trans. Graph. 22(3): 453-462 (2003)
- [c11]Serdar Tasiran, Yuan Yu, Brannon Batson: Using a formal specification and a model checker to monitor and direct simulation. DAC 2003: 356-361
- 2002
- [j2]Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani, Serdar Tasiran: An assume-guarantee rule for checking simulation. ACM Trans. Program. Lang. Syst. 24(1): 51-64 (2002)
- [c10]Shaz Qadeer, Serdar Tasiran: Promising Directions in Hardware Design Verification (invited). ISQED 2002: 381-387
- 2001
- [j1]Serdar Tasiran, Kurt Keutzer: Coverage Metrics for Functional Validation of Hardware Designs. IEEE Design & Test of Computers 18(4): 36-45 (2001)
- [c9]Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer: A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage. ICCD 2001: 82-88
1990 – 1999
- 1999
- [c8]Ellen Sentovich, David L. Dill, Serdar Tasiran: Formal verification meets simulation (tutorial abstract). ICCAD 1999: 221
- 1998
- [c7]Rajeev Alur, Thomas A. Henzinger, Freddy Y. C. Mang, Shaz Qadeer, Sriram K. Rajamani, Serdar Tasiran: MOCHA: Modularity in Model Checking. CAV 1998: 521-525
- [c6]Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani, Serdar Tasiran: An Assume-Guarantee Rule for Checking Simulation. FMCAD 1998: 421-432
- 1997
- [c5]Serdar Tasiran, Robert K. Brayton: STARI: A Case Study in Compositional and Hierarchical Timing Verification. CAV 1997: 191-201
- 1996
- [c4]Serdar Tasiran, Rajeev Alur, Robert P. Kurshan, Robert K. Brayton: Verifying Abstractions of Timed Systems. CONCUR 1996: 546-562
- 1995
- [c3]Serdar Tasiran, Ramin Hojati, Robert K. Brayton: Language containment of non-deterministic omega-automata. CHARME 1995: 261-277
- 1994
- [c2]Adnan Aziz, Serdar Tasiran, Robert K. Brayton: BDD Variable Ordering for Interacting Finite State Machines. DAC 1994: 283-288
- [c1]Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: HSIS: A BDD-Based Environment for Formal Verification. DAC 1994: 454-459
Coauthor Index
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last updated on 2013-01-31 19:41 CET by the dblp team