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 | 2013 | |
|---|---|---|
| c32 |      | |
| 2012 | ||
| j13 | | Jianchao Lu, Xiaomi Mao, Baris Taskin: Integrated Clock Mesh Synthesis With Incremental Register Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 31(2): 217-227 (2012) |
| j12 | | Jianchao Lu, Ying Teng, Baris Taskin: A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs. IEEE Trans. VLSI Syst. 20(6): 1002-1011 (2012) |
| j11 | | Vinayak Honkote, Baris Taskin: ZeROA: Zero Clock Skew Rotary Oscillatory Array. IEEE Trans. VLSI Syst. 20(8): 1528-1532 (2012) |
| c31 | | Ying Teng, Baris Taskin: Synchronization scheme for brick-based rotary oscillator arrays. ACM Great Lakes Symposium on VLSI 2012: 117-122 |
| c30 | | Jianchao Lu, Xiaomi Mao, Baris Taskin: Clock mesh synthesis with gated local trees and activity driven register clustering. ICCAD 2012: 691-697 |
| c29 | | Matthew R. Guthaus, Baris Taskin: High-Performance, Low-Power Resonant Clocking: Embedded tutorial. ICCAD 2012: 742-745 |
| c28 | | |
| c27 | | |
| c26 | | Ankit More, Baris Taskin: A unified design methodology for a hybrid wireless 2-D NoC. ISCAS 2012: 640-643 |
| c25 | | Vinayak Honkote, Ankit More, Baris Taskin: 3-D Parasitic Modeling for Rotary Interconnects. VLSI Design 2012: 137-142 |
| 2011 | ||
| j10 | | Shannon M. Kurtas, Baris Taskin: Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling. Journal of Circuits, Systems, and Computers 20(5): 881-898 (2011) |
| j9 | | Jianchao Lu, Baris Taskin: Clock buffer polarity assignment with skew tuning. ACM Trans. Design Autom. Electr. Syst. 16(4): 49 (2011) |
| j8 | | Vinayak Honkote, Baris Taskin: CROA: Design and Analysis of the Custom Rotary Oscillatory Array. IEEE Trans. VLSI Syst. 19(10): 1837-1847 (2011) |
| c24 | | Jianchao Lu, Vinayak Honkote, Xin Chen, Baris Taskin: Steiner tree based rotary clock routing with bounded skew and capacitive load balancing. DATE 2011: 455-460 |
| c23 | | Ankit More, Baris Taskin: EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs. ICCD 2011: 19-24 |
| c22 | | Ying Teng, Jianchao Lu, Baris Taskin: ROA-brick topology for rotary resonant clocks. ICCD 2011: 273-278 |
| c21 | | Jianchao Lu, Yusuf Aksehir, Baris Taskin: Register On MEsh (ROME): A novel approach for clock mesh network synthesis. ISCAS 2011: 1219-1222 |
| c20 | | Jianchao Lu, Baris Taskin: Reconfigurable clock polarity assignment for peak current reduction of clock-gated circuits. ISCAS 2011: 1940-1943 |
| c19 | | Jianchao Lu, Xiaomi Mao, Baris Taskin: Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis. ISPD 2011: 131-138 |
| c18 | | Ying Teng, Baris Taskin: Process variation sensitivity of the Rotary Traveling Wave Oscillator. ISQED 2011: 236-242 |
| c17 | | Ankit More, Baris Taskin: Simulation based study of on-chip antennas for a reconfigurable hybrid 2D wireless network-on-chip. SLIP 2011: 1 |
| 2010 | ||
| j7 | | Ying Teng, Baris Taskin: Look-Up Table Based Low Power Rotary Traveling Wave Oscillator Design Considering the Skin Effect. J. Low Power Electronics 6(4): 491-502 (2010) |
| j6 | | |
| c16 | | Ankit More, Baris Taskin: Electromagnetic interaction of on-chip antennas and CMOS metal layers for wireless IC interconnects. ACM Great Lakes Symposium on VLSI 2010: 413-416 |
| c15 | | Vinayak Honkote, Baris Taskin: Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array. ICCD 2010: 209-214 |
| c14 | | Vinayak Honkote, Baris Taskin: PEEC based parasitic modeling for power analysis on custom rotary rings. ISLPED 2010: 111-116 |
| c13 | | Ankit More, Baris Taskin: Leakage current analysis for intra-chip wireless interconnects. ISQED 2010: 49-53 |
| c12 | | Vinayak Honkote, Baris Taskin: Skew analysis and bounded skew constraint methodology for rotary clocking technology. ISQED 2010: 413-417 |
| c11 | | Jianchao Lu, Baris Taskin: Clock buffer polarity assignment considering capacitive load. ISQED 2010: 765-770 |
| c10 | | Jianchao Lu, Baris Taskin: Clock Tree Synthesis with XOR Gates for Polarity Assignment. ISVLSI 2010: 17-22 |
| c9 | | Ankit More, Baris Taskin: Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs. ISVLSI 2010: 228-231 |
| c8 | | Ankit More, Baris Taskin: Simulation based study of wireless RF interconnects for practical CMOs implementation. SLIP 2010: 35-42 |
| c7 | | Ankit More, Baris Taskin: Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC. SoCC 2010: 447-452 |
| c6 | | Vinayak Honkote, Baris Taskin: Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array. VLSI Design 2010: 218-223 |
| 2009 | ||
| j5 | | Baris Taskin, Ivan S. Kourtev: Multi-Phase Rotary Clock Synchronization of Level-Sensitive Circuits. Journal of Circuits, Systems, and Computers 18(5): 899-908 (2009) |
| j4 | | Baris Taskin, Andy Chiu, Jonathan Salkind, Daniel Venutolo: A shift-register-based QCA memory architecture. JETC 5(1) (2009) |
| j3 | | Baris Taskin, Joseph Demaio, Owen Farell, Michael Hazeltine, Ryan Ketner: Custom topology rotary clock router with tree subnetworks. ACM Trans. Design Autom. Electr. Syst. 14(3) (2009) |
| c5 | | Vinayak Honkote, Baris Taskin: Zero clock skew synchronization with rotary clocking technology. ISQED 2009: 588-593 |
| 2008 | ||
| c4 | | |
| 2006 | ||
| j2 | | Baris Taskin, Ivan S. Kourtev: Delay Insertion Method in Clock Skew Scheduling. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 651-663 (2006) |
| 2005 | ||
| c3 | | |
| 2004 | ||
| j1 |  | Baris Taskin, Ivan S. Kourtev: Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. IEEE Trans. VLSI Syst. 12(1): 12-27 (2004) |
| c2 | | Baris Taskin, Ivan S. Kourtev: Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits. ISCAS (2) 2004: 617-620 |
| 2002 | ||
| c1 | | Baris Taskin, Ivan S. Kourtev: Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 111-118 |
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