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Hannu Tenhunen
2010 – today
- 2013
[j37]Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels. J. Comput. Syst. Sci. 79(4): 440-456 (2013)- [j36]Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture. J. Comput. Syst. Sci. 79(4): 475-491 (2013)
- [j35]Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: A systematic reordering mechanism for on-chip networks using efficient congestion-aware method. Journal of Systems Architecture - Embedded Systems Design 59(4-5): 213-222 (2013)
- [c149]Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila, Hannu Tenhunen: CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems. DATE 2013: 1048-1051
- [c148]Syed M. A. H. Jafri, Ozan Bag, Ahmed Hemani, Nasim Farahini, Kolin Paul, Juha Plosila, Hannu Tenhunen: Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells. ISQED 2013: 104-111
- [c147]Sanaz Rahimi Moosavi, Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Enhancing Performance of 3D Interconnection Networks using Efficient Multicast Communication Protocol. PDP 2013: 294-301
- [c146]Masoumeh Ebrahimi, Xin Chang, Masoud Daneshtalab, Juha Plosila, Pasi Liljeberg, Hannu Tenhunen: DyXYZ: Fully Adaptive Routing Algorithm for 3D NoCs. PDP 2013: 499-503
- 2012
- [j34]Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Khalid Latif, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Design and management of high-performance, reliable and thermal-aware 3D networks-on-chip. IET Circuits, Devices & Systems 6(5): 308-321 (2012)
- [j33]Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen: Skewing-based method for reduction of functional crosstalk and power supply noise caused by on-chip buses. IET Computers & Digital Techniques 6(2): 114-124 (2012)
- [j32]Liang Guang, Ethiopia Nigussie, Juha Plosila, Hannu Tenhunen: Dual Monitoring Communication for Self-Aware Network-on-Chip: Architecture and Case Study. IJARAS 3(3): 72-91 (2012)
- [j31]Liang Guang, Ethiopia Nigussie, Juha Plosila, Jouni Isoaho, Hannu Tenhunen: Survey of Self-Adaptive NoCs with Energy-Efficiency and Dependability. IJERTCS 3(2): 1-22 (2012)
- [j30]Tapio Pahikkala, Antti Airola, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen, Tapio Salakoski: Parallelized Online Regularized Least-Squares for Adaptive Embedded Systems. IJERTCS 3(2): 73-91 (2012)
- [j29]Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Exploring a Low-Cost and Power-Efficient Hybridization Technique for 3D NoC-Bus Hybrid Architecture Using LastZ-Based Routing Algorithms. J. Low Power Electronics 8(4): 403-414 (2012)
- [j28]Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Memory-Efficient On-Chip Network With Adaptive Interfaces. IEEE Trans. on CAD of Integrated Circuits and Systems 31(1): 146-159 (2012)
- [j27]Geng Yang, Li Xie, Matti Mäntysalo, Jian Chen, Hannu Tenhunen, Li-Rong Zheng: Bio-Patch Design and Implementation Based on a Low-Power System-on-Chip and Paper-Based Inkjet Printing Technology. IEEE Transactions on Information Technology in Biomedicine 16(6): 1043-1050 (2012)
- [j26]Sampo Tuuna, Ethiopia Nigussie, Jouni Isoaho, Hannu Tenhunen: Modeling of Energy Dissipation in RLC Current-Mode Signaling. IEEE Trans. VLSI Syst. 20(6): 1146-1151 (2012)
- [j25]Ethiopia Nigussie, Sampo Tuuna, Juha Plosila, Jouni Isoaho, Hannu Tenhunen: Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput. IEEE Trans. VLSI Syst. 20(12): 2265-2277 (2012)
- [c145]Amir-Mohammad Rahmani, Khalid Latif, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: ARB-NET: A novel adaptive monitoring platform for stacked mesh 3D NoC architectures. ASP-DAC 2012: 413-418
- [c144]Moazzam Fareed Niazi, Tiberiu Seceleanu, Hannu Tenhunen: Towards Reuse-Based Development for the On-chip Distributed SoC Architecture. COMPSAC Workshops 2012: 278-283
- [c143]Khalid Latif, Amir-Mohammad Rahmani, Pasi Liljeberg, Hannu Tenhunen, Tiberiu Seceleanu: A Cluster-Based Core Protection Technique for Networks-on-Chip. COMPSAC 2012: 360-361
- [c142]Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks. DATE 2012: 320-325
- [c141]Geng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng: A multi-parameter bio-electric ASIC sensor with integrated 2-wire data transmission protocol for wearable healthcare system. DATE 2012: 443-448
- [c140]Liang Guang, Ethiopia Nigussie, Juha Plosila, Jouni Isoaho, Hannu Tenhunen: HLS-DoNoC: High-level simulator for dynamically organizational NoCs. DDECS 2012: 89-94
- [c139]Khalid Latif, Amir-Mohammad Rahmani, Tiberiu Seceleanu, Hannu Tenhunen: Designing a High Performance and Reliable Networks-on-Chip Using Network Interface Assisted Routing Strategy. DSD 2012: 34-41
- [c138]Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Hannu Tenhunen: MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip. DSD 2012: 201-207
- [c137]Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Power and Thermal Analysis of Stacked Mesh 3D NoC Using AdaptiveXYZ Routing Algorithm. DSD 2012: 208-215
- [c136]Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen: Energy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic Classes. DSD 2012: 242-249
- [c135]Thomas Canhao Xu, Tapio Pahikkala, Antti Airola, Pasi Liljeberg, Juha Plosila, Tapio Salakoski, Hannu Tenhunen: Implementation and Analysis of Block Dense Matrix Decomposition on Network-on-Chips. HPCC-ICESS 2012: 516-523
- [c134]Liang Guang, Ethiopia Nigussie, Juha Plosila, Hannu Tenhunen: Vertical and horizontal integration towards collective adaptive system: a visionary approach. UbiComp 2012: 762-765
- [c133]Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Hannu Tenhunen: Dual Congestion Awareness scheme in On-Chip Networks. NESEA 2012: 1-6
- [c132]Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: An Efficient Hybridization Scheme for Stacked Mesh 3D NoC Architecture. PDP 2012: 507-514
- [c131]Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: LEAR - A Low-Weight and Highly Adaptive Routing Method for Distributing Congestions in On-chip Networks. PDP 2012: 520-524
- [c130]Syed M. A. H. Jafri, Liang Guang, Axel Jantsch, Kolin Paul, Ahmed Hemani, Hannu Tenhunen: Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation. PECCS 2012: 450-458
- 2011
- [j24]Ethiopia Nigussie, Sampo Tuuna, Juha Plosila, Pasi Liljeberg, Jouni Isoaho, Hannu Tenhunen: Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects. IET Circuits, Devices & Systems 5(6): 505-517 (2011)
- [j23]Masoud Daneshtalab, Masoumeh Ebrahimi, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen: A generic adaptive path-based routing method for MPSoCs. Journal of Systems Architecture - Embedded Systems Design 57(1): 109-120 (2011)
- [j22]Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen: A study of 3D Network-on-Chip design for data parallel H.264 coding. Microprocessors and Microsystems - Embedded Hardware Design 35(7): 603-612 (2011)
- [j21]Khalid Latif, Tiberiu Seceleanu, Cristina Cerschi Seceleanu, Hannu Tenhunen: Service based communication for MPSoC platform-SegBus. Microprocessors and Microsystems - Embedded Hardware Design 35(7): 643-655 (2011)
- [j20]Zhuo Zou, David S. Mendoza, Peng Wang, Qin Zhou, Jia Mao, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng: A Low-Power and Flexible Energy Detection IR-UWB Receiver for RFID and Wireless Sensor Networks. IEEE Trans. on Circuits and Systems 58-I(7): 1470-1482 (2011)
- [c129]Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architectures. 3DIC 2011: 1-8
- [c128]Alexander W. Yin, Thomas Canhao Xu, Bo Yang, Pasi Liljeberg, Hannu Tenhunen: Change Function of 2D/3D Network-on-Chip. CIT 2011: 181-188
- [c127]Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Cluster-based topologies for 3D stacked architectures. Conf. Computing Frontiers 2011: 14
- [c126]Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen: Optimal memory controller placement for chip multiprocessor. CODES+ISSS 2011: 217-226
- [c125]Khalid Latif, Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Tiberiu Seceleanu, Pasi Liljeberg, Hannu Tenhunen: Enhancing Performance of NoC-Based Architectures Using Heuristic Virtual-Channel Sharing Approach. COMPSAC 2011: 442-447
- [c124]Rajeev Kumar Kanth, Pasi Liljeberg, Hannu Tenhunen, Qiansu Wan, Yasar Amin, Botao Shao, Qiang Chen, Li-Rong Zheng, Harish Kumar: Evaluating Sustainability, Environmental Assessment and Toxic Emissions during Manufacturing Process of RFID Based Systems. DASC 2011: 1066-1071
- [c123]Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen: Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip. DDECS 2011: 105-110
- [c122]Khalid Latif, Amir-Mohammad Rahmani, Ethiopia Nigussie, Hannu Tenhunen, Tiberiu Seceleanu: A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip. DFT 2011: 454-462
- [c121]Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture. DSD 2011: 173-180
- [c120]Khalid Latif, Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Tiberiu Seceleanu, Pasi Liljeberg, Hannu Tenhunen: Enhancing Performance Sustainability of Fault Tolerant Routing Algorithms in NoC-Based Architectures. DSD 2011: 626-633
- [c119]Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen: Study of Hierarchical N-Body Methods for Network-on-Chip Architectures. Euro-Par Workshops (2) 2011: 365-374
- [c118]Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen: Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures. FPT 2011: 1-6
- [c117]Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen: A Minimal Average Accessing Time Scheduler for Multicore Processors. ICA3PP (2) 2011: 287-299
- [c116]Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen: Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures. IPDPS Workshops 2011: 290-293
- [c115]Amir-Mohammad Rahmani, Khalid Latif, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Power-Efficient Inter-Layer Communication Architectures for 3D NoC. ISVLSI 2011: 355-356
- [c114]Amir-Mohammad Rahmani, Pasi Liljeberg, Khalid Latif, Juha Plosila, Kameswar Rao Vaddina, Hannu Tenhunen: Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures. NOCS 2011: 65-72
- [c113]Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model. NOCS 2011: 73-80
- [c112]Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels. PATMOS 2011: 278-287
- [c111]Amir-Mohammad Rahmani, Khalid Latif, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication. PDP 2011: 423-430
- [c110]Khalid Latif, Amir-Mohammad Rahmani, Liang Guang, Tiberiu Seceleanu, Hannu Tenhunen: PVS-NoC: Partial Virtual Channel Sharing NoC Architecture. PDP 2011: 470-477
- [c109]Liang Guang, Bo Yang, Juha Plosila, Jouni Isoaho, Hannu Tenhunen: Hierarchical Agent Monitoring Design Platform - Towards Self-aware and Adaptive Embedded Systems. PECCS 2011: 573-581
- [c108]Tapio Pahikkala, Antti Airola, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen, Tapio Salakoski: A Parallel Online Regularized Least-squares Machine Learning Algorithm for Future Multi-core Processors. PECCS 2011: 590-599
- [c107]Rajeev Kumar Kanth, Pasi Liljeberg, Hannu Tenhunen, Qiansu Wan, Waqar Ahmad, Li-Rong Zheng, Harish Kumar: Insight into the Requirements of Self-aware, Adaptive and Reliable Embedded Sub-systems of Satellite Spacecraft. PECCS 2011: 603-608
- [c106]Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: High-performance on-chip network platform for memory-on-processor architectures. ReCoSoC 2011: 1-6
- [c105]Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Efficient congestion-aware selection method for on-chip networks. ReCoSoC 2011: 1-4
- [c104]Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Agent-based on-chip network using efficient selection method. VLSI-SoC 2011: 284-289
- 2010
- [j19]Liang Guang, Juha Plosila, Jouni Isoaho, Hannu Tenhunen: Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and its Formal Specification. IJERTCS 1(2): 86-105 (2010)
- [j18]Liang Guang, Ethiopia Nigussie, Jouni Isoaho, Pekka Rantala, Hannu Tenhunen: Interconnection alternatives for hierarchical monitoring communication in parallel SoCs. Microprocessors and Microsystems - Embedded Hardware Design 34(5): 118-128 (2010)
- [j17]Liang Guang, Ethiopia Nigussie, Pekka Rantala, Jouni Isoaho, Hannu Tenhunen: Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip. ACM Trans. Embedded Comput. Syst. 9(3) (2010)
- [c103]Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: CMIT - A novel cluster-based topology for 3D stacked architectures. 3DIC 2010: 1-5
- [c102]Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen: Operating System Processor Scheduler Design for Future Chip Multiprocessor. ARCS Workshops 2010: 69-76
- [c101]Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs. Conf. Computing Frontiers 2010: 267-276
- [c100]Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen: On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. DATE 2010: 1325-1328
- [c99]Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Developing reconfigurable FIFOs to optimize power/performance of Voltage/Frequency Island-based networks-on-chip. DDECS 2010: 105-110
- [c98]Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen: Partitioning methods for unicast/multicast traffic in 3D NoC architecture. DDECS 2010: 127-132
- [c97]Khalid Latif, Tiberiu Seceleanu, Hannu Tenhunen: Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers. ECBS 2010: 131-138
- [c96]Moazzam Fareed Niazi, Hannu Tenhunen, Tiberiu Seceleanu: An Emulation Solution for the SegBus Platform. ECBS 2010: 268-275
- [c95]Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen: A Greedy Heuristic Approximation Scheduling Algorithm for 3D Multicore Processors. Euro-Par Workshops (1) 2010: 281-291
- [c94]Khalid Latif, Tiberiu Seceleanu, Cristina Cerschi Seceleanu, Hannu Tenhunen: Resource-aware task allocation and scheduling for segbus platform. ICECS 2010: 523-526
- [c93]Khalid Latif, Amir-Mohammad Rahmani, Tiberiu Seceleanu, Hannu Tenhunen: Power- and performance-aware IP mapping for NoC-based MPSoC platforms. ICECS 2010: 758-761
- [c92]Moazzam Fareed Niazi, Tiberiu Seceleanu, Hannu Tenhunen: A Performance Estimation Technique for the SegBus Distributed Architecture. ICPP Workshops 2010: 89-98
- [c91]Amir-Mohammad Rahmani, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen: Power-aware NoC router using central forecasting-based dynamic virtual channel allocation. ISCAS 2010: 3224-3227
- [c90]Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Input-Output Selection Based Router for Networks-on-Chip. ISVLSI 2010: 92-97
- [c89]Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels. ISVLSI 2010: 452-453
- [c88]Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: High-Performance TSV Architecture for 3-D ICs. ISVLSI 2010: 467-468
- [c87]Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen: Performance Analysis of 3D NoCs Partitioning Methods. ISVLSI 2010: 479-480
- [c86]Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: A Low-Latency and Memory-Efficient On-chip Network. NOCS 2010: 99-106
- [c85]Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen: HAMUM - A Novel Routing Protocol for Unicast and Multicast Traffic in MPSoCs. PDP 2010: 525-532
- [c84]Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing. PDP 2010: 546-550
- [c83]Moazzam Fareed Niazi, Tiberiu Seceleanu, Hannu Tenhunen: An automated control code generation approach for the SegBus platform. SoCC 2010: 199-204
- [c82]Liang Guang, Ethiopia Nigussie, Hannu Tenhunen: Run-time communication bypassing for energy-efficient, low-latency per-core DVFS on Network-on-Chip. SoCC 2010: 481-486
2000 – 2009
- 2009
- [j16]Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 28(8): 1237-1250 (2009)
- [c81]Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen, Li-Rong Zheng: Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. 3DIC 2009: 1-8
- [c80]Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerasekera, Hannu Tenhunen: 3-D memory organization and performance analysis for multi-processor network-on-chip architecture. 3DIC 2009: 1-7
- [c79]Matthew J. Turnquist, Erkka Laulainen, Jani Mäkipää, Hannu Tenhunen, Lauri Koskinen: Adaptive Sub-Threshold Test Circuit. AHS 2009: 197-203
- [c78]Liang Guang, Ethiopia Nigussie, Lauri Koskinen, Hannu Tenhunen: Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication. ARCS 2009: 183-194
- [c77]Geng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng: An ASIC Solution for Intelligent Electrodes and Active-Cable used in a Wearable ECG Monitoring System. BIODEVICES 2009: 209-213
- [c76]Masoumeh Ebrahimi, Masoud Daneshtalab, Mohammad Hossein Neishaburi, Siamak Mohammadi, Ali Afzali-Kusha, Juha Plosila, Hannu Tenhunen: An efficent dynamic multicast routing protocol for distributing traffic in NOCs. DATE 2009: 1064-1069
- [c75]Alexander Wei Yin, Liang Guang, Ethiopia Nigussie, Pasi Liljeberg, Jouni Isoaho, Hannu Tenhunen: Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks. DSD 2009: 141-146
- [c74]Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen: An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs. DSD 2009: 203-206
- [c73]Majid Baghaei Nejad, David S. Mendoza, Zhuo Zou, Soheil Radiom, Georges G. E. Gielen, Li-Rong Zheng, Hannu Tenhunen: A remote-powered RFID tag with 10Mb/s UWB uplink and -18.5dBm sensitivity UHF downlink in 0.18µm CMOS. ISSCC 2009: 198-199
- [c72]Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen: Scalability of network-on-chip communication architecture for 3-D meshes. NOCS 2009: 114-123
- [c71]Alexander Wei Yin, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen: Explorations of Honeycomb Topologies for Network-on-Chip. NPC 2009: 73-79
- [c70]Geng Yang, Jian Chen, Hannu Tenhunen, Li-Rong Zheng: Intelligent electrode design for long-term ECG monitoring at home: Prototype design using FPAA and FPGA. PervasiveHealth 2009: 1-4
- [c69]Moazzam Fareed Niazi, Khalid Latif, Hannu Tenhunen, Tiberiu Seceleanu: A DSL for the SegBus platform. SoCC 2009: 393-398
- 2008
- [j15]Adam Strak, Andreas Gothenberg, Hannu Tenhunen: Power-Supply and Substrate-Noise-Induced Timing Jitter in Nonoverlapping Clock Generation Circuits. IEEE Trans. on Circuits and Systems 55-I(4): 1041-1054 (2008)
- [j14]Elena Dubrova, Maxim Teslenko, Hannu Tenhunen: A Computational Scheme Based on Random Boolean Networks. T. Comp. Sys. Biology 10: 41-58 (2008)
- [j13]Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. IEEE Trans. VLSI Syst. 16(5): 589-593 (2008)
- [j12]Sampo Tuuna, Li-Rong Zheng, Jouni Isoaho, Hannu Tenhunen: Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid. IEEE Trans. VLSI Syst. 16(6): 766-770 (2008)
- [c68]Elena Dubrova, Maxim Teslenko, Hannu Tenhunen: On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers. DATE 2008: 1286-1291
- [c67]Dragos Truscan, Tiberiu Seceleanu, Johan Lilius, Hannu Tenhunen: A Model-Based Design Process for the SegBus Distributed Architecture. ECBS 2008: 307-316
- [c66]Khalid Latif, Moazzam Fareed Niazi, Hannu Tenhunen, Tiberiu Seceleanu, Sakir Sezer: Application development flow for on-chip distributed architectures. SoCC 2008: 163-168
- [c65]Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen: Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation. VLSI Design 2008: 228-234
- 2007
- [j11]Zhuo Zou, Majid Baghaei Nejad, Hannu Tenhunen, Li-Rong Zheng: An efficient passive RFID system for ubiquitous identification and sensing using impulse UWB radio. Elektrotechnik und Informationstechnik 124(11): 397-403 (2007)
- [c64]Yuechao Niu, Majid Baghaei Nejad, Hannu Tenhunen, Li-Rong Zheng: Design of a Digital Baseband Processor for UWB Transceiver on RFID Tag. AINA Workshops (2) 2007: 358-361
- [c63]Dragos Truscan, Tiberiu Seceleanu, Hannu Tenhunen, Johan Lilius: Towards a Design Methodology for Multiprocessor Platforms. COMPSAC (1) 2007: 575-578
- [c62]Pekka Rantala, Jouni Isoaho, Hannu Tenhunen: Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip. DSD 2007: 551-555
- [c61]Pekka Rantala, Jouni Isoaho, Hannu Tenhunen: Agent-Based Reconfigurability for Fault-Tolerance in Network-on-Chip. ERSA 2007: 207-210
- [c60]Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen: Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. ICCAD 2007: 212-219
- [c59]Majid Baghaei Nejad, Zhuo Zou, Hannu Tenhunen, Li-Rong Zheng: A Novel Passive Tag with Asymmetric Wireless Link for RFID and WSN Applications. ISCAS 2007: 1593-1596
- [c58]Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen: Early selection of system implementation choice among SoC, SoP and 3-D Integration. SoCC 2007: 187-190
- [c57]Zhuo Zou, Majid Baghaei Nejad, Hannu Tenhunen, Li-Rong Zheng: Baseband design for passive semi-UWB wireless sensor and identification systems. SoCC 2007: 313-316
- [c56]Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Delay-Balanced Smart Repeaters for On-Chip Global Signaling. VLSI Design 2007: 308-313
- 2006
- [j10]Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen: Analytical model for crosstalk and intersymbol interference in point-to-point buses. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1400-1410 (2006)
- [c55]Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. SLIP 2006: 113-120
- [c54]Tiberiu Seceleanu, Axel Jantsch, Hannu Tenhunen: On-Chip Distributed Architectures. SoCC 2006: 329-330
- 2005
- [j9]Ahmed Amine Jerraya, Hannu Tenhunen, Wayne Wolf: Guest Editors' Introduction: Multiprocessor Systems-on-Chips. IEEE Computer 38(7): 36-40 (2005)
- [j8]Meigen Shen, Jian Liu, Li-Rong Zheng, Esa Tjukanoff, Hannu Tenhunen: Robustness enhancement through chip-package co-design for high-speed electronics. Microelectronics Journal 36(9): 846-855 (2005)
- [j7]Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen: Modeling delay and noise in arbitrarily coupled RC trees. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1725-1739 (2005)
- [c53]Elena Dubrova, Maxim Teslenko, Hannu Tenhunen: Computing attractors in dynamic networks. IADIS AC 2005: 535-542
- [c52]Meigen Shen, Li-Rong Zheng, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen: Case study of interconnect analysis for standing wave oscillator design. ISCAS (1) 2005: 456-459
- [c51]Xinzhong Duo, Li-Rong Zheng, Mohammed Ismail, Hannu Tenhunen: A concurrent multi-band LNA for multi-standard radios. ISCAS (4) 2005: 3982-3985
- [c50]Meigen Shen, Li-Rong Zheng, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen: Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach. ISQED 2005: 573-578
- [c49]Ana Rusu, Mohammed Ismail, Hannu Tenhunen: A Modified Cascaded Sigma-Delta Modulator with Improved Linearity. ISVLSI 2005: 77-82
- [c48]Jari Nurmi, Jan Madsen, Erwin Ofner, Jouni Isoaho, Hannu Tenhunen: The SoC-Mobinet Model in System-on-Chip Education. MSE 2005: 71-72
- [c47]Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen: Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. PATMOS 2005: 277-285
- 2004
- [j6]Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen: A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. Integration 38(1): 3-17 (2004)
- [j5]Axel Jantsch, Johnny Öberg, Hannu Tenhunen: Special issue on networks on chip. Journal of Systems Architecture 50(2-3): 61-63 (2004)
- [j4]Jian Liu, Li-Rong Zheng, Hannu Tenhunen: Interconnect intellectual property for Network-on-Chip (NoC). Journal of Systems Architecture 50(2-3): 65-79 (2004)
- [j3]Imed Ben Dhaou, Hannu Tenhunen: Efficient library characterization for high-level power estimation. IEEE Trans. VLSI Syst. 12(6): 657-661 (2004)
- [c46]Andreas Gothenberg, Hannu Tenhunen: Performance analysis of sampling switches in voltage and frequency domains using Volterra series. ISCAS (1) 2004: 765-768
- [c45]Xinzhong Duo, Li-Rong Zheng, Hannu Tenhunen: RF robustness enhancement through statistical analysis of chip package co-design. ISCAS (1) 2004: 988-991
- [c44]Meigen Shen, Li-Rong Zheng, Hannu Tenhunen: Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics. ISQED 2004: 184-189
- [c43]Adam Strak, Hannu Tenhunen: Suppression of Jitter Effects in A/D Converters through Sigma-Delta Sampling. ISVLSI 2004: 121-126
- [c42]Ana Rusu, Alexei Borodenkov, Mohammed Ismail, Hannu Tenhunen: Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers. PATMOS 2004: 564-573
- [c41]Jian Liu, Li-Rong Zheng, Hannu Tenhunen: A circuit-switched network architecture for network-on-chip. SoCC 2004: 55-58
- 2003
- [j2]Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Maximizing throughput over parallel wire structures in the deep submicrometer regime. IEEE Trans. VLSI Syst. 11(2): 224-243 (2003)
- [c40]Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen: Analytic Modeling of Interconnects for Deep Sub-Micron Circuits. ICCAD 2003: 835-842
- [c39]Meigen Shen, Li-Rong Zheng, Hannu Tenhunen: Case study of cost and performance trade-off analysis for mixed-signal integration in system-on-chip. ISCAS (5) 2003: 585-588
- [c38]Wim Michielsen, Li-Rong Zheng, Hannu Tenhunen: Analysis and design of a double tuned Clapp oscillator for multi-band multi-standard radio. ISCAS (1) 2003: 681-684
- [c37]Jian Liu, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen: A global wire planning scheme for Network-on-Chip. ISCAS (4) 2003: 892-895
- [c36]Jian Liu, Meigen Shen, Li-Rong Zheng, Hannu Tenhunen: System level interconnect design for network-on-chip using interconnect IPs. SLIP 2003: 117-124
- 2002
- [c35]Tuomas Valtonen, Jouni Isoaho, Hannu Tenhunen: The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance. FPL 2002: 816-825
- [c34]
- [c33]Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Optimising bandwidth over deep sub-micron interconnect. ISCAS (4) 2002: 193-196
- [c32]Tuomas Valtonen, Tero Nurmi, Jouni Isoaho, Hannu Tenhunen: Interconnection of autonomous error-tolerant cells. ISCAS (4) 2002: 473-476
- [c31]Pasi Liljeberg, Imed Ben Dhaou, Juha Plosila, Jouni Isoaho, Hannu Tenhunen: Interconnect peak current reduction for wavelet array processor using self-timed signaling. ISCAS (4) 2002: 485-488
- [c30]Bingxin Li, Hannu Tenhunen: A structure of cascading multi-bit modulators without dynamic element matching or digital correction. ISCAS (3) 2002: 711-714
- [c29]Dinesh Pamunuwa, Hannu Tenhunen: On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects. ISQED 2002: 240-245
- 2001
- [c28]Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi: Energy efficient signaling in DSM CMOS technology. ISCAS (5) 2001: 411-414
- [c27]Bingxin Li, Hannu Tenhunen: Sigma delta modulators using semi-uniform quantizers. ISCAS (1) 2001: 456-459
- [c26]Imed Ben Dhaou, N. Money, Hannu Tenhunen: Fast low-power characterization of arithmetic units in DSM CMOS. ISCAS (5) 2001: 531-534
- [c25]T. Suutari, Jouni Isoaho, Hannu Tenhunen: High-speed serial communication with error correction using 0.25 um CMOS technology. ISCAS (4) 2001: 618-621
- [c24]Imed Ben Dhaou, Elena Dubrova, Hannu Tenhunen: Power Efficient Inter-Module Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology. ISMVL 2001: 61-66
- [c23]Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi: Energy Efficient Signaling in Deep Submicron CMOS Technology. ISQED 2001: 319-324
- [c22]Peeter Ellervee, Hannu Tenhunen: Digital Hardware Organization Course for SoC Program. MSE 2001: 26-27
- [c21]Peter Nilsson, Petru Eles, Hannu Tenhunen: SOCWARE: A New Swedish Design Cluster for System-on-Chip. MSE 2001: 44-45
- [c20]Hannu Tenhunen, Elena Dubrova: SoC Masters: An International M.Sc. Program in System-on-Chip Design at KTH. MSE 2001: 64-66
- [c19]Dinesh Pamunuwa, Hannu Tenhunen: Repeater Insertion To Minimise Delay In Coupled Interconnects. VLSI Design 2001: 513-517
- 2000
- [c18]Imed Ben Dhaou, Hannu Tenhunen: Energy efficient high-speed on-chip signaling in deep-submicron CMOS technology. SLIP 2000: 69-76
1990 – 1999
- 1999
- [c17]Li-Rong Zheng, Hannu Tenhunen: Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits. ARVLSI 1999: 123-136
- [c16]Bingxin Li, Hannu Tenhunen: A Design of Operational Amplifier for Sigma Delta Modulators Using 0.35um CMOS Process. VLSI 1999: 23-34
- [c15]P. Eriksson, Hannu Tenhunen: A model for predicting sampler RF bandwidth and conversion loss. ISCAS (6) 1999: 18-21
- [c14]Imed Ben Dhaou, Hannu Tenhunen: Combinatorial architectural level power optimization for a class of orthogonal transforms. ISCAS (1) 1999: 70-75
- [c13]Lihong Jia, Yonghong Gao, Jouni Isoaho, Hannu Tenhunen: Design of a super-pipelined Viterbi decoder. ISCAS (1) 1999: 133-136
- [c12]B. E. Jonsson, Hannu Tenhunen: A dual 3-V 32-MS/s CMOS switched-current ADC for telecommunication applications. ISCAS (2) 1999: 343-346
- [c11]B. E. Jonsson, Hannu Tenhunen: A 3 V switched-current pipelined analog-to-digital converter in a 5 V CMOS process. ISCAS (2) 1999: 351-354
- [c10]L. Horvath, Imed Ben Dhaou, Hannu Tenhunen, Jouni Isoaho: A novel, high-speed, reconfigurable demapper-symbol deinterleaver architecture for DVB-T. ISCAS (4) 1999: 382-385
- [c9]Thomas Meincke, Ahmed Hemani, Shashi Kumar, Peeter Ellervee, Johnny Öberg, Thomas Olsson, Peter Nilsson, Dan Lindqvist, Hannu Tenhunen: Globally asynchronous locally synchronous architecture for large high-performance ASICs. ISCAS (2) 1999: 512-515
- [c8]Li-Rong Zheng, Hannu Tenhunen: Effective power and ground distribution scheme for deep submicron high speed VLSI circuits. ISCAS (1) 1999: 537-540
- 1996
- [c7]Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen: A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts. VLSI Design 1996: 23-28
- 1995
- [c6]M. Rinne, T. Jarske, Hannu Tenhunen, Olli Vainio, Yrjö Neuvo: Noise Suppression System Integration Using an Analog Allpass Filter Bank. ISCAS 1995: 1207-1210
- 1994
- [c5]Axel Jantsch, Peeter Ellervee, Ahmed Hemani, Johnny Öberg, Hannu Tenhunen: Hardware/software partitioning and minimizing memory interface traffic. EURO-DAC 1994: 226-231
- [c4]T. Saluvere, D. Kerek, Hannu Tenhunen: Direct Sequence Spread Spectrum Digital Radio DSP Prototyping Using Xilinx FPGAs. FPL 1994: 138-140
- [c3]Jouni Isoaho, Axel Jantsch, Hannu Tenhunen: DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques. FPL 1994: 318-320
- 1993
- [j1]Jouni Isoaho, Jari Pasanen, Olli Vainio, Hannu Tenhunen: DSP system integration and prototyping with FPGAS. VLSI Signal Processing 6(2): 155-172 (1993)
- 1992
- [c2]Jouni Isoaho, Arto Nummela, Hannu Tenhunen: Technologies and Utilization fo Field Programmable Gate Arrays. FPL 1992: 11-25
- 1991
- [c1]Eero Pajarre, Tapani Ritoniemi, Hannu Tenhunen: Methods and Algorithms for Converting IC Designs Between Incompatible Design Systems. ICCD 1991: 34-37
Coauthor Index
[j37] [j36] [j35] [c147] [c146] [j34] [j30] [j29] [j28] [c145] [c143] [c142] [c137] [c135] [c132] [c131] [j24] [j23] [j22] [c129] [c128] [c127] [c126] [c125] [c124] [c123] [c121] [c120] [c119] [c117] [c115] [c114] [c113] [c112] [c111] [c108] [c107] [c106] [c105] [c104] [c103] [c102] [c101] [c99] [c98] [c95] [c91] [c90] [c89] [c88] [c87] [c86] [c85] [c84] [c75] [c74] [c71] [c31]
[j37] [j36] [j35] [c149] [c148] [c147] [c146] [j34] [j32] [j31] [j29] [j28] [j25] [c145] [c142] [c140] [c138] [c137] [c136] [c135] [c134] [c133] [c132] [c131] [j24] [c129] [c127] [c121] [c118] [c116] [c115] [c114] [c113] [c112] [c111] [c109] [c106] [c105] [c104] [j19] [c103] [c101] [c99] [c90] [c89] [c88] [c86] [c84] [c76] [c31]
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last updated on 2013-06-12 21:34 CEST by the dblp team