Parthasarathy P. Tirumalai

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	1992
c5		Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler: Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. ISMVL 1992: 66-74
c4		B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai: Code generation schema for modulo scheduled loops. MICRO 1992: 158-169
c3		B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker: Register Allocation for Software Pipelined Loops. PLDI 1992: 283-299
	1991
j2		Parthasarathy P. Tirumalai, Jon T. Butler: Minimization Algorithms for Multiple-Valued Programmable Logic Arrays. IEEE Trans. Computers 40(2): 167-177 (1991)
j1		Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker: Parallelization of WHILE loops on pipelined architectures. The Journal of Supercomputing 5(2-3): 119-136 (1991)
c2		Parthasarathy P. Tirumalai, Varadarajan G. Vadakkencherry: Parallel Algorithms for Minimizing Multiple-Valued Programmable Logic Arrays. ISMVL 1991: 287-295
	1990
c1		Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker: Parallelization of loops with exits on pipelined architectures. SC 1990: 200-212

Coauthor Index

1	Jon T. Butler	[c5] [j2]
2	Gerhard W. Dueck	[c5]
3	Robert C. Earle	[c5]
4	Meng Lee	[c3] [j1] [c1]
5	B. Ramakrishna Rau	[c4] [c3]
6	Michael S. Schlansker	[c4] [c3] [j1] [c1]
7	Varadarajan G. Vadakkencherry	[c2]

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