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Nozomu Togawa
2010 – today
- 2013
[j28]Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa: A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation. IEICE Transactions 96-A(1): 312-321 (2013)- [j27]Masashi Tawada, Masao Yanagisawa, Nozomu Togawa: A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. IEICE Transactions 96-A(6): 1283-1292 (2013)
- [c41]Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, Masao Yanagisawa: Suspicious timing error prediction with in-cycle clock gating. ISQED 2013: 335-340
- 2012
- [j26]Seungju Lee, Masao Yanagisawa, Nozomu Togawa: A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores. IEICE Transactions 95-A(9): 1538-1549 (2012)
- [j25]Youhua Shi, Nozomu Togawa, Masao Yanagisawa: Scan-Based Attack on AES through Round Registers and Its Countermeasure. IEICE Transactions 95-A(12): 2338-2346 (2012)
- [j24]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. IEEE Trans. VLSI Syst. 20(1): 176-181 (2012)
- [c40]Seungju Lee, Nozomu Togawa, Yusuke Sekihara, Takashi Aoki, Akira Onozawa: A hybrid NoC architecture utilizing packet transmission priority control method. APCCAS 2012: 404-407
- [c39]Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa: Scan-based attack against DES cryptosystems using scan signatures. APCCAS 2012: 599-602
- [c38]Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa: Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. APCCAS 2012: 603-606
- [c37]Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa: State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit. APCCAS 2012: 607-610
- [c36]Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa: An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures. ISCAS 2012: 576-579
- [c35]Seungju Lee, Nozomu Togawa, Takashi Aoki, Akira Onozawa: A novel BMNoC configuration algorithm utilizing communication volume and locality among cores. ISCAS 2012: 1668-1671
- 2011
- [j23]Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto: Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint. IEICE Transactions 94-A(4): 1082-1090 (2011)
- [j22]Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto: Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint. IEICE Transactions 94-A(12): 2482-2489 (2011)
- 2010
- [j21]Ryuta Nara, Kei Satoh, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa: Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures. IEICE Transactions 93-A(12): 2481-2489 (2010)
- [j20]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Improved Launch for Higher TDF Coverage With Fewer Test Patterns. IEEE Trans. on CAD of Integrated Circuits and Systems 29(8): 1294-1299 (2010)
- [c34]Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Scan-based attack against elliptic curve cryptosystems. ASP-DAC 2010: 407-412
- [c33]Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. ISCAS 2010: 921-924
- [c32]Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: State-dependent changeable scan architecture against scan-based side channel attacks. ISCAS 2010: 1867-1870
2000 – 2009
- 2009
- [j19]Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: An L1 Cache Design Space Exploration System for Embedded Applications. IEICE Transactions 92-A(6): 1442-1453 (2009)
- [j18]Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n). IEICE Transactions 92-A(9): 2304-2317 (2009)
- [j17]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction. IEICE Transactions 92-A(12): 3119-3127 (2009)
- [j16]Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures. IEICE Transactions 92-A(12): 3169-3179 (2009)
- [j15]Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A Scan-Based Attack Based on Discriminators for AES Cryptosystems. IEICE Transactions 92-A(12): 3229-3237 (2009)
- [j14]Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A Two-Level Cache Design Space Exploration System for Embedded Applications. IEICE Transactions 92-A(12): 3238-3247 (2009)
- [c31]Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Exact and fast L1 cache simulation for embedded systems. ASP-DAC 2009: 817-822
- [c30]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Design-for-secure-test for crypto cores. ITC 2009: 1
- 2008
- [j13]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A Secure Test Technique for Pipelined Advanced Encryption Standard. IEICE Transactions 91-D(3): 776-780 (2008)
- [j12]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique. IEICE Transactions 91-A(4): 1054-1061 (2008)
- [j11]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss. IEICE Transactions 91-A(12): 3514-3523 (2008)
- [c29]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: GECOM: Test data compression combined with all unknown response masking. ASP-DAC 2008: 577-582
- [c28]Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). ASP-DAC 2008: 697-702
- 2007
- [c27]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. ISCAS 2007: 149-152
- [c26]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Power-efficient LDPC code decoder architecture. ISLPED 2007: 359-362
- 2006
- [j10]Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier. IEICE Transactions 89-C(3): 243-249 (2006)
- [j9]Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule. IEICE Transactions 89-A(4): 969-978 (2006)
- [j8]Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki: Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Transactions 89-A(4): 996-1004 (2006)
- [j7]Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule. IEICE Transactions 89-A(12): 3602-3612 (2006)
- [c25]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Memory-Efficient Accelerating Schedule for LDPC Decoder. APCCAS 2006: 1317-1320
- [c24]Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. ASP-DAC 2006: 594-599
- [c23]Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki: FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC 2006: 653-658
- [c22]Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: A parallel LSI architecture for LDPC decoder improving message-passing schedule. ISCAS 2006
- 2005
- [j6]Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. IEICE Transactions 88-A(4): 876-884 (2005)
- [j5]Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki: A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. IEICE Transactions 88-D(7): 1340-1349 (2005)
- [j4]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving. IEICE Transactions 88-D(7): 1526-1537 (2005)
- [c21]Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A processor core synthesis system in IP-based SoC design. ASP-DAC 2005: 286-291
- [c20]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Reconfigurable adaptive FEC system with interleaving. ASP-DAC 2005: 1252-1255
- [c19]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura: Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium 2005: 386-389
- [c18]Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa: Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. ICCD 2005: 503-510
- [c17]Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki: Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. ISCAS (4) 2005: 3499-3502
- 2004
- [c16]Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A thread partitioning algorithm in low power high-level synthesis. ASP-DAC 2004: 74-79
- [c15]Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A cosynthesis algorithm for application specific processors with heterogeneous datapaths. ASP-DAC 2004: 250-255
- [c14]Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki: Instruction set and functional unit synthesis for SIMD processor cores. ASP-DAC 2004: 743-750
- [c13]Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium 2004: 432-437
- 2003
- [c12]Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki: A hardware/software partitioning algorithm for SIMD processor cores. ASP-DAC 2003: 135-140
- 2002
- [c11]Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. APCCAS (1) 2002: 171-176
- [c10]Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: VLSI Architecture for a Flexible Motion Estimation with Parameters. VLSI Design 2002: 452-457
- 2001
- [c9]Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Area/delay estimation for digital signal processor cores. ASP-DAC 2001: 156-161
- 2000
- [c8]Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki: An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). ASP-DAC 2000: 309-312
1990 – 1999
- 1999
- [j3]Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki: A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization. Journal of Circuits, Systems, and Computers 9(1-2): 09-112 (1999)
- [c7]Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki: A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. ASP-DAC 1999: 335-338
- 1998
- [j2]Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 803-818 (1998)
- [c6]Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki: A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. ASP-DAC 1998: 265-274
- [c5]Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki: An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. ASP-DAC 1998: 519-526
- 1997
- [j1]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki: A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Multi-FPGA Systems. Journal of Circuits, Systems, and Computers 7(5): 373-394 (1997)
- [c4]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki: A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. ASP-DAC 1997: 569-578
- 1995
- [c3]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki: Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization. ASP-DAC 1995
- 1994
- [c2]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki: A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. ICCAD 1994: 156-163
- [c1]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki: A Simultaneous Placement and Global Routing Algorithm for FPGAs. ISCAS 1994: 483-486
Coauthor Index
[j28] [j27] [c41] [j26] [j25] [j24] [c39] [c38] [c37] [c36] [j23] [j22] [j21] [j20] [c34] [c33] [c32] [j19] [j18] [j17] [j16] [j15] [j14] [c31] [c30] [j13] [j11] [c29] [c28] [c27] [j10] [j8] [c24] [c23] [j6] [j5] [c21] [c19] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [j3] [c7] [j2] [c6] [c5]
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last updated on 2013-06-18 22:44 CEST by the dblp team