Thomas Toifl

Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf: A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS. ISSCC 2013: 310-311

Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf: An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS. ISSCC 2013: 408-409

Lukas Kull, Thomas Toifl, Martin Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici: A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS. ISSCC 2013: 468-469

Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Daniel Dreps, Troy J. Beukema, Andrea Prati, Daniele Gardellini, Marcel A. Kossel, Peter Buchmann, Matthias Braendli, Pier Andrea Francese, Thomas Morf: A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. J. Solid-State Circuits 47(4): 897-910 (2012)

John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, W. R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman: A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. J. Solid-State Circuits 47(12): 3232-3248 (2012)

John F. Bulzacchelli, Troy J. Beukema, Daniel Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman: A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. ISSCC 2012: 324-326

Christian Menolfi, Juergen Hertle, Thomas Toifl, Thomas Morf, Daniele Gardellini, Matthias Braendli, Peter Buchmann, Marcel A. Kossel: A 28Gb/s source-series terminated TX in 32nm CMOS SOI. ISSCC 2012: 334-336

Rajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu: A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. ISSCC 2011: 152-154

Christian Menolfi, Thomas Toifl, Michael Ruegg, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Morf: A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI. ISSCC 2011: 156-158

Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin Schmatz: A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS. J. Solid-State Circuits 45(12): 2850-2860 (2010)

Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin Schmatz: A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS. ISSCC 2010: 160-161

Devesh Nema, Thomas Toifl: Active compensation of supply noise for a 5-GHz VCO in 45-nm CMOS SOI technology. ISCAS 2008: 2617-2620

Thomas Toifl, Martin Schmatz, Christian Menolfi: Low-Complexity Adaptive Equalization for High-Speed Chip-to-Chip Communication Paths by Zero-Forcing of Jitter Components. IEEE Transactions on Communications 54(9): 1554-1557 (2006)