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Josep Torrellas
2010 – today
- 2013
[c124]Wonsun Ahn, Yuelu Duan, Josep Torrellas: DeAliaser: alias speculation using atomic region support. ASPLOS 2013: 167-180- [c123]Nima Honarmand, Nathan Dautenhahn, Josep Torrellas, Samuel T. King, Gilles Pokam, Cristiano Pereira: Cyrus: unintrusive application-level record-replay for replay parallelism. ASPLOS 2013: 193-206
- [c122]Xuehai Qian, Josep Torrellas, Benjamin Sahelices, Depei Qian: Volition: scalable and precise sequential consistency violation detection. ASPLOS 2013: 535-548
- [c121]Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard Lethin, Benoît Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, Jianping Xu: Runnemede: An architecture for Ubiquitous High-Performance Computing. HPCA 2013: 198-209
- [c120]Aditya Agrawal, Prabhat Jain, Amin Ansari, Josep Torrellas: Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies. HPCA 2013: 400-411
- [c119]Amin Ansari, Shuguang Feng, Shantanu Gupta, Josep Torrellas, Scott A. Mahlke: Illusionist: Transforming lightweight cores into aggressive cores on demand. HPCA 2013: 436-447
- [c118]Ulya R. Karpuzcu, Abhishek A. Sinkar, Nam Sung Kim, Josep Torrellas: EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing. HPCA 2013: 542-553
- 2012
- [j29]Josep Torrellas: 2012 International Symposium on Computer Architecture Influential Paper Award. IEEE Micro 32(5): 4-5 (2012)
- [c117]Ulya R. Karpuzcu, Krishna B. Kolluru, Nam Sung Kim, Josep Torrellas: VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages. DSN 2012: 1-11
- [c116]Xuehai Qian, Benjamin Sahelices, Josep Torrellas: BulkSMT: Designing SMT processors for atomic-block execution. HPCA 2012: 153-164
- [c115]Shanxiang Qi, Norimasa Otsuki, Lois Orosa Nogueira, Abdullah Muzahid, Josep Torrellas: Pacman: Tolerating asymmetric data races with unintrusive hardware. HPCA 2012: 349-360
- [c114]Yuelu Duan, Xing Zhou, Wonsun Ahn, Josep Torrellas: BulkCompactor: Optimized deterministic execution via Conflict-Aware commit of atomic blocks. HPCA 2012: 361-372
- [c113]Josep Torrellas: FlexRAM: Toward an advanced Intelligent Memory system: A retrospective paper. ICCD 2012: 3-4
- [c112]Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Pratap Pattnaik, Josep Torrellas: FlexRAM: Toward an advanced Intelligent Memory system. ICCD 2012: 5-14
- [c111]Ehsan Totoni, Babak Behzad, Swapnil Ghike, Josep Torrellas: Comparing the power and performance of Intel's SCC to state-of-the-art CPUs and GPUs. ISPASS 2012: 78-87
- [c110]Abdullah Muzahid, Shanxiang Qi, Josep Torrellas: Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically. MICRO 2012: 363-375
- 2011
- [c109]Rishi Agarwal, Josep Torrellas: FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes. ISCA 2011: 33-44
- [c108]Rishi Agarwal, Pranav Garg, Josep Torrellas: Rebound: scalable checkpointing for coherent shared memory. ISCA 2011: 153-164
- [r2]Josep Torrellas: Cache-Only Memory Architecture (COMA). Encyclopedia of Parallel Computing 2011: 216-220
- [r1]
- 2010
- [c107]Brian Greskamp, Ulya R. Karpuzcu, Josep Torrellas: LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores. HPCA 2010: 1-12
- [c106]Josep Torrellas, Bill Gropp, Vivek Sarkar, Jaime H. Moreno, Kunle Olukotun: Extreme scale computing: Challenges and opportunities. HPCA 2010: 1
- [c105]Adrian Nistor, Darko Marinov, Josep Torrellas: InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing. MICRO 2010: 251-262
- [c104]Abdullah Muzahid, Norimasa Otsuki, Josep Torrellas: AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection. MICRO 2010: 287-297
- [c103]Xuehai Qian, Wonsun Ahn, Josep Torrellas: ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment. MICRO 2010: 447-458
- [c102]Josep Torrellas, Bill Gropp, Jaime H. Moreno, Kunle Olukotun, Vivek Sarkar: Extreme scale computing: challenges and opportunities. PPOPP 2010: 101-102
2000 – 2009
- 2009
- [j28]Derek Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, Josep Torrellas: Two hardware-based approaches for deterministic multiprocessor replay. Commun. ACM 52(6): 93-100 (2009)
- [j27]Josep Torrellas, Luis Ceze, James Tuck, Calin Cascaval, Pablo Montesinos, Wonsun Ahn, Milos Prvulovic: The Bulk Multicore architecture for improved programmability. Commun. ACM 52(12): 58-65 (2009)
- [j26]
- [j25]James Tuck, Wonsun Ahn, Josep Torrellas, Luis Ceze: SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization. IEEE Micro 29(1): 84-95 (2009)
- [c101]Pablo Montesinos, Matthew Hicks, Samuel T. King, Josep Torrellas: Capo: a software-hardware interface for practical deterministic multiprocessor replay. ASPLOS 2009: 73-84
- [c100]Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles: Blueshift: Designing processors for timing speculation from the ground up. HPCA 2009: 213-224
- [c99]
- [c98]Abdullah Muzahid, Darío Suárez Gracia, Shanxiang Qi, Josep Torrellas: SigRace: signature-based data race detection. ISCA 2009: 337-348
- [c97]Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Torrellas, J.-W. Lee, Xing Fang, Samuel P. Midkiff, David Wong: BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support. MICRO 2009: 133-144
- [c96]Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas: The BubbleWrap many-core: popping cores for sequential acceleration. MICRO 2009: 447-458
- [c95]Adrian Nistor, Darko Marinov, Josep Torrellas: Light64: lightweight hardware support for data race detection during systematic testing of parallel programs. MICRO 2009: 541-552
- 2008
- [c94]Luis Ceze, Christoph von Praun, Calin Cascaval, Pablo Montesinos, Josep Torrellas: Concurrency control with data coloring. MSPC 2008: 6-10
- [c93]James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas: SoftSig: software-exposed hardware signatures for code analysis and optimization. ASPLOS 2008: 145-156
- [c92]Pablo Montesinos, Luis Ceze, Josep Torrellas: DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Effciently. ISCA 2008: 289-300
- [c91]Radu Teodorescu, Josep Torrellas: Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors. ISCA 2008: 363-374
- [c90]Abhishek Tiwari, Josep Torrellas: Facelift: Hiding and slowing down aging in multicores. MICRO 2008: 129-140
- [c89]Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas: EVAL: Utilizing processors with variation-induced timing errors. MICRO 2008: 423-434
- 2007
- [j24]Smruti R. Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, Josep Torrellas: Patching Processor Design Errors with Programmable Hardware. IEEE Micro 27(1): 12-25 (2007)
- [c88]Brian Greskamp, Josep Torrellas: Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking. PACT 2007: 213-224
- [c87]Pablo Montesinos, Wei Liu, Josep Torrellas: Using Register Lifetime Predictions to Protect Register Files against Soft Errors. DSN 2007: 286-296
- [c86]Luis Ceze, Pablo Montesinos, Christoph von Praun, Josep Torrellas: Colorama: Architectural Support for Data-Centric Synchronization. HPCA 2007: 133-144
- [c85]James Tuck, Wei Liu, Josep Torrellas: CAP: Criticality analysis for power-efficient speculative multithreading. ICCD 2007: 409-416
- [c84]Luis Ceze, James Tuck, Pablo Montesinos, Josep Torrellas: BulkSC: bulk enforcement of sequential consistency. ISCA 2007: 278-289
- [c83]Abhishek Tiwari, Smruti R. Sarangi, Josep Torrellas: ReCycle: : pipeline adaptation to tolerate process variation. ISCA 2007: 323-334
- [c82]Brian Greskamp, Smruti R. Sarangi, Josep Torrellas: Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates. ISCAS 2007: 1261-1264
- [c81]Smruti R. Sarangi, Brian Greskamp, Josep Torrellas: A Model for Timing Errors in Processors with Parameter Variation. ISQED 2007: 647-654
- [c80]Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas: Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. MICRO 2007: 27-42
- [c79]Karin Strauss, Xiaowei Shen, Josep Torrellas: Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors. MICRO 2007: 327-342
- [c78]Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau: Estimating design time for system circuits. VLSI-SoC 2007: 60-65
- 2006
- [j23]Josep Torrellas: Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences. IEEE Micro 26(1): 8-9 (2006)
- [j22]Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas: Energy-Efficient Thread-Level Speculation. IEEE Micro 26(1): 80-91 (2006)
- [j21]Radu Teodorescu, Jun Nakano, Josep Torrellas: SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback. IEEE Micro 26(5): 28-40 (2006)
- [j20]Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau: CAVA: Using checkpoint-assisted value prediction to hide L2 misses. TACO 3(2): 182-208 (2006)
- [c77]Paul Sack, Brian E. Bliss, Zhiqiang Ma, Paul Petersen, Josep Torrellas: Accurate and efficient filtering for the Intel thread checker race detector. ASID 2006: 34-41
- [c76]Smruti R. Sarangi, Brian Greskamp, Josep Torrellas: CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging. DSN 2006: 301-312
- [c75]Jun Nakano, Pablo Montesinos, Kourosh Gharachorloo, Josep Torrellas: ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers. HPCA 2006: 200-211
- [c74]Luis Ceze, James Tuck, Josep Torrellas, Calin Cascaval: Bulk Disambiguation of Speculative Threads in Multiprocessors. ISCA 2006: 227-238
- [c73]Karin Strauss, Xiaowei Shen, Josep Torrellas: Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors. ISCA 2006: 327-338
- [c72]Smruti R. Sarangi, Abhishek Tiwari, Josep Torrellas: Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware. MICRO 2006: 26-37
- [c71]Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, Josep Torrellas: PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection. MICRO 2006: 38-52
- [c70]James Tuck, Luis Ceze, Josep Torrellas: Scalable Cache Miss Handling for High Memory-Level Parallelism. MICRO 2006: 409-422
- [c69]Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas: POSH: a TLS compiler that exploits program structure. PPOPP 2006: 158-167
- [e2]Josep Torrellas (Ed.): Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, ASID 2006, San Jose, California, USA, October 21, 2006. ACM 2006, ISBN 1-59593-576-2
- [e1]Josep Torrellas, Siddhartha Chatterjee (Eds.): Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2006, New York, New York, USA, March 29-31, 2006. ACM 2006, ISBN 1-59593-189-9
- 2005
- [j19]Yuanyuan Zhou, Pin Zhou, Feng Qin, Wei Liu, Josep Torrellas: Efficient and flexible architectural support for dynamic monitoring. TACO 2(1): 3-33 (2005)
- [j18]María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas: Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. TACO 2(3): 247-279 (2005)
- [c68]Radu Teodorescu, Josep Torrellas: Prototyping Architectural Support for Program Rollback Using FPGAs. FCCM 2005: 23-32
- [c67]Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas: Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation. ICS 2005: 179-188
- [c66]Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas: Thread-Level Speculation on a CMP can be energy efficient. ICS 2005: 219-228
- 2004
- [j17]Luis Ceze, Karin Strauss, James Tuck, Jose Renau, Josep Torrellas: CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction. Computer Architecture Letters 3 (2004)
- [j16]Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas: iWatcher: Simple, General Architectural Support for Software Debugging. IEEE Micro 24(6): 50-56 (2004)
- [c65]Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas: iWatcher: Efficient Architectural Support for Software Debugging. ISCA 2004: 224-237
- [c64]Pin Zhou, Wei Liu, Long Fei, Shan Lu, Feng Qin, Yuanyuan Zhou, Samuel P. Midkiff, Josep Torrellas: AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants. MICRO 2004: 269-280
- 2003
- [j15]José F. Martínez, Josep Torrellas: Speculative Synchronization: Programmability and Performance for Parallel Codes. IEEE Micro 23(6): 126-134 (2003)
- [j14]Yan Solihin, Jaejin Lee, Josep Torrellas: Correlation Prefetching with a User-Level Memory Thread. IEEE Trans. Parallel Distrib. Syst. 14(6): 563-580 (2003)
- [c63]María Jesús Garzarán, Milos Prvulovic, Víctor Viñals, José María Llabería, Lawrence Rauchwerger, Josep Torrellas: Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. IEEE PACT 2003: 170-181
- [c62]Anthony-Trung Nguyen, Josep Torrellas: Design Trade-Offs in High-Throughput Coherence Controllers. IEEE PACT 2003: 194-205
- [c61]María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas: Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. HPCA 2003: 191-202
- [c60]Milos Prvulovic, Josep Torrellas: ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes. ISCA 2003: 110-121
- [c59]Michael C. Huang, Jose Renau, Josep Torrellas: Positional Adaptation of Processors: Application to Energy Reduction. ISCA 2003: 157-168
- [c58]Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas: Programming the FlexRAM parallel intelligent memory system. PPOPP 2003: 49-60
- 2002
- [j13]Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Mateo Valero, Josep Torrellas: Software Trace Cache for Commercial Applications. International Journal of Parallel Programming 30(5): 373-395 (2002)
- [c57]José F. Martínez, Josep Torrellas: Speculative synchronization: applying thread-level speculation to explicitly parallel applications. ASPLOS 2002: 18-29
- [c56]Marcelo H. Cintra, Josep Torrellas: Speculative Multithreading Eliminating Squashes through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors. HPCA 2002: 43-54
- [c55]Francis H. Dang, María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Alin Jula, Hao Yu, Nancy M. Amato, Lawrence Rauchwerger, Josep Torrellas: SmartApps: An Application Centric Approach to High Performance Computing: Compiler-Assisted Software and Hardware Support for Reduction Operations. IPDPS 2002
- [c54]Milos Prvulovic, Josep Torrellas, Zheng Zhang: ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors. ISCA 2002: 111-122
- [c53]Yan Solihin, Josep Torrellas, Jaejin Lee: Using a User-Level Memory Thread for Correlation Prefetching. ISCA 2002: 171-182
- [c52]Michael C. Huang, Jose Renau, Josep Torrellas: Energy-efficient hybrid wakeup logic. ISLPED 2002: 196-201
- [c51]José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas: Cherry: checkpointed early resource recycling in out-of-order microprocessors. MICRO 2002: 3-14
- 2001
- [j12]Venkata Krishnan, Josep Torrellas: The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. International Journal of Parallel Programming 29(1): 3-33 (2001)
- [j11]Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas: The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management. J. Instruction-Level Parallelism 3 (2001)
- [j10]Yan Solihin, Jaejin Lee, Josep Torrellas: Automatic Code Mapping on an Intelligent Memory Architecture. IEEE Trans. Computers 50(11): 1248-1266 (2001)
- [c50]María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Josep Torrellas, Alin Jula, Hao Yu, Lawrence Rauchwerger: Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors. IEEE PACT 2001: 243-254
- [c49]Jaejin Lee, Yan Solihin, Josep Torrellas: Automatically Mapping Code on an Intelligent Memory Architecture. HPCA 2001: 121-132
- [c48]Milos Prvulovic, María Jesús Garzarán, Lawrence Rauchwerger, Josep Torrellas: Removing architectural bottlenecks to the scalability of speculative parallelization. ISCA 2001: 204-215
- [c47]Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas: L1 data cache decomposition for energy efficiency. ISLPED 2001: 10-15
- 2000
- [c46]Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen: Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration. HPCA 2000: 15-25
- [c45]Qiang Cao, Josep Torrellas, H. V. Jagadish: Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation. ICCD 2000: 175-186
- [c44]Yan Solihin, Jaejin Lee, Josep Torrellas: Adaptively Mapping Code in an Intelligent Memory Architecture. Intelligent Memory Systems 2000: 71-84
- [c43]Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas: Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. Intelligent Memory Systems 2000: 152-159
- [c42]Marcelo H. Cintra, José F. Martínez, Josep Torrellas: Architectural support for scalable speculative parallelization in shared-memory multiprocessors. ISCA 2000: 13-24
- [c41]Lawrence Rauchwerger, Nancy M. Amato, Josep Torrellas: SmartApps: An Application Centric Approach to High Performance Computing. LCPC 2000: 82-96
- [c40]Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas: A framework for dynamic energy efficiency and temperature management. MICRO 2000: 202-213
1990 – 1999
- 1999
- [j9]Fredrik Dahlgren, Josep Torrellas: Cache-Only Memory Architectures. IEEE Computer 32(6): 72-79 (1999)
- [j8]Zheng Zhang, Marcelo H. Cintra, Josep Torrellas: Excel-NUMA: Toward Programmability, Simplicity, and High Performance. IEEE Trans. Computers 48(2): 256-264 (1999)
- [j7]Chun Xia, Josep Torrellas: Comprehensive Hardware and Software Support for Operating Systems to Exploit. IEEE Trans. Computers 48(5): 494-505 (1999)
- [j6]Venkata Krishnan, Josep Torrellas: A Chip-Multiprocessor Architecture with Speculative Multithreading. IEEE Trans. Computers 48(9): 866-880 (1999)
- [c39]Venkata Krishnan, Josep Torrellas: The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. IEEE PACT 1999: 24-33
- [c38]Ye Zhang, Lawrence Rauchwerger, Josep Torrellas: Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors. HPCA 1999: 135-139
- [c37]Russell M. Clapp, Ashwini K. Nanda, Josep Torrellas: Second Workshop on Computer Architecture Evaluation Using Commercial Workloads. HPCA 1999: 322
- [c36]Qiang Cao, Josep Torrellas, Pedro Trancoso, Josep-Lluis Larriba-Pey, Bob Knighten, Youjip Won: Detailed Characterization of a Quad Pentium Pro Server Running TPC-D. ICCD 1999: 108-
- [c35]Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Josep Torrellas, Pratap Pattnaik: FlexRAM: Toward an Advanced Intelligent Memory System. ICCD 1999: 192-201
- [c34]Pedro Trancoso, Josep Torrellas: Cache Optimization for Memory-Resident Decision Support Commercial Workloads. ICCD 1999: 546-
- [c33]David Koufaty, Josep Torrellas: Compiler Support for Data Forwarding in Scalable Shared-Memory Multiprocessors. ICPP 1999: 181-
- [c32]Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas: Optimization of Instruction Fetch for Decision Support Workloads. ICPP 1999: 238-245
- [c31]Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Josep Torrellas, Mateo Valero: Software trace cache. International Conference on Supercomputing 1999: 119-126
- [c30]José F. Martínez, Josep Torrellas, José Duato: Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivity. International Conference on Supercomputing 1999: 202-209
- [c29]Josep Torrellas: Upcoming Architectural Advances in DSM Machines and Their Impact on Programmability. PPSC 1999
- [c28]Josep Torrellas, Yan Solihin, Vinh Vi Lam: Scal-Tool: Pinpointing and Quantifying Scalability Bottlenecks in DSM Multiprocessors. SC 1999: 17
- 1998
- [j5]Josep Torrellas, Chun Xia, Russell L. Daigle: Optimizing the Instruction Cache Performance of the Operating System. IEEE Trans. Computers 47(12): 1363-1381 (1998)
- [c27]Venkata Krishnan, Josep Torrellas: An Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors. IEEE PACT 1998: 286-293
- [c26]Sujoy Basu, Josep Torrellas: Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma. HPCA 1998: 152-161
- [c25]Ye Zhang, Lawrence Rauchwerger, Josep Torrellas: Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors. HPCA 1998: 162-173
- [c24]
- [c23]David Koufaty, Josep Torrellas: Comparing Data Forwarding and Prefetching for Communication-induced Misses in Shared-memory MPs. International Conference on Supercomputing 1998: 53-60
- [c22]Venkata Krishnan, Josep Torrellas: Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-multiprocessor. International Conference on Supercomputing 1998: 85-92
- [c21]Venkata Krishnan, Josep Torrellas: A Clustered Approach to Multithreaded Processors. IPPS/SPDP 1998: 627-634
- 1997
- [j4]Josep Torrellas, Zheng Zhang: The Performance of the Cedar Multistage Switching Network. IEEE Trans. Parallel Distrib. Syst. 8(4): 321-336 (1997)
- [c20]Liuxi Yang, Josep Torrellas: Speeding up the Memory Hierarchy in Flat COMA Multiprocessors. HPCA 1997: 4-13
- [c19]Pedro Trancoso, Josep-Lluis Larriba-Pey, Zheng Zhang, Josep Torrellas: The Memory Performance of DSS Commercial Workloads in Shared-Memory Multiprocessors. HPCA 1997: 250-260
- [c18]Zheng Zhang, Josep Torrellas: Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA. HPCA 1997: 272-281
- 1996
- [j3]David Koufaty, Xiangfeng Chen, David K. Poulsen, Josep Torrellas: Data Forwarding in Scalable Shared-Memory Multiprocessors. IEEE Trans. Parallel Distrib. Syst. 7(12): 1250-1264 (1996)
- [c17]
- [c16]Alain Raynaud, Zheng Zhang, Josep Torrellas: Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors. HPCA 1996: 323-334
- [c15]Anthony-Trung Nguyen, Maged M. Michael, Arun Sharma, Josep Torrellas: The Augmint multiprocessor simulation toolkit for Intel x86 architectures. ICCD 1996: 486-490
- [c14]Pedro Trancoso, Josep Torrellas: The Impact of Speeding up Critical Sections with Data Prefetching and Forwarding. ICPP, Vol. 3 1996: 79-86
- [c13]Liuxi Yang, Josep Torrellas: Optimizing Primary Data Caches for Parallel Scientific Applications: The Pool Buffer Approach. International Conference on Supercomputing 1996: 141-148
- [c12]
- 1995
- [j2]Josep Torrellas, Andrew Tucker, Anoop Gupta: Evaluating the Performance of Cache-Affinity Scheduling in Shared-Memory Multiprocessors. J. Parallel Distrib. Comput. 24(2): 139-151 (1995)
- [c11]Josep Torrellas, Chun Xia, Russell L. Daigle: Optimizing Instruction Cache Performance for Operating System Intensive Workloads. HPCA 1995: 360-369
- [c10]David Koufaty, Xiangfeng Chen, David K. Poulsen, Josep Torrellas: Data Forwarding in Scalable Shared-Memory Multiprocessors. International Conference on Supercomputing 1995: 255-264
- [c9]Zheng Zhang, Josep Torrellas: Speeding Up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching. ISCA 1995: 188-199
- 1994
- [j1]Josep Torrellas, Monica S. Lam, John L. Hennessy: False Sharing ans Spatial Locality in Multiprocessor Caches. IEEE Trans. Computers 43(6): 651-663 (1994)
- [c8]Josep Torrellas, David Koufaty, David A. Padua: Comparing the Performance of the DASH and CEDAR Multiprocessors. ICPP 1994: 304-308
- [c7]Josep Torrellas, Zheng Zhang: The performance of the Cedar multistage switching network. SC 1994: 265-274
- [c6]Ding-Kai Chen, Josep Torrellas, Pen-Chung Yew: An efficient algorithm for the run-time parallelization of DOACROSS loops. SC 1994: 518-527
- 1993
- [c5]Josep Torrellas, Andrew Tucker, Anoop Gupta: Benefits of Cache-Affinity Scheduling in Shared-Memory Multiprocessors: A Summary. SIGMETRICS 1993: 272-274
- 1992
- [c4]Josep Torrellas, Anoop Gupta, John L. Hennessy: Characterizing the Caching and Synchronization Performance of a Multiprocessor Operating System. ASPLOS 1992: 162-174
- 1990
- [c3]Josep Torrellas, John L. Hennessy: Estimating the Performance Advantages of Relaxing Consistency in a Shared Memory Multiprocessor. ICPP (1) 1990: 26-34
- [c2]Josep Torrellas, Monica S. Lam, John L. Hennessy: Share Data Placement Optimizations to Reduce Multiprocessor Cache Miss Rates. ICPP (2) 1990: 266-270
- [c1]Josep Torrellas, John L. Hennessy, Thierry Weil: Analysis of Critical Architectural and Program Parameters in a Hierarchical Shared Memory Multiprocessor. SIGMETRICS 1990: 163-172
Coauthor Index
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last updated on 2013-06-11 21:39 CEST by the dblp team