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 | 2012 | |
|---|---|---|
| j18 |      | Amine Dehbaoui, Victor Lomné, Thomas Ordas, Lionel Torres, Michel Robert, Philippe Maurine: Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence. IEEE Trans. VLSI Syst. 20(3): 573-577 (2012) |
| c107 | | Guilherme Perin, Lionel Torres, Pascal Benoit, Philippe Maurine: Amplitude demodulation-based EM analysis of different RSA implementations. DATE 2012: 1167-1172 |
| c106 | | Florian Devic, Lionel Torres, Jérémie Crenne, Benoît Badrignans, Pascal Benoit: SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration. FPL 2012: 57-62 |
| c105 | | Pascal Cotret, Florian Devic, Guy Gogniat, Benoît Badrignans, Lionel Torres: Security enhancements for FPGA-based MPSoCs: A boot-to-runtime protection flow for an embedded Linux-based system. ReCoSoC 2012: 1-8 |
| 2011 | ||
| j17 | | Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres: A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines. IEEE Design & Test of Computers 28(5): 62-71 (2011) |
| j16 | | Gabriel Marchesan Almeida, Rémi Busseuil, Luciano Ost, Florent Bruguier, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert: PI and PID Regulation Approaches for Performance-Constrained Adaptive Multiprocessor System-on-Chip. Embedded Systems Letters 3(3): 77-80 (2011) |
| p1 | | Lionel Torres, Pascal Benoit, Gilles Sassatelli, Michel Robert, Fabien Clermidy, Diego Puschini: An Introduction to Multi-Core System on Chip - Trends and Challenges. Multiprocessor System-on-Chip 2011: 1-21 |
| c104 | | Florent Bruguier, Pascal Benoit, Philippe Maurine, Lionel Torres: A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis. FPL 2011: 20-23 |
| c103 | | Lyonel Barthe, Luis Vitório Cargnini, Pascal Benoit, Lionel Torres: Optimizing an Open-Source Processor for FPGAs: A Case Study. FPL 2011: 551-556 |
| c102 | | Lionel Torres, Weisheng Zhao: Magnetic memory (MRAM), a new area for 2D and 3D SoC/SiP design. ACM Great Lakes Symposium on VLSI 2011: 429-430 |
| c101 | | Weisheng Zhao, Lionel Torres, Yoann Guillemenet, Luis Vitório Cargnini, Yahya Lakys, Jacques-Olivier Klein, Dafine Ravelosona, Gilles Sassatelli, Claude Chappert: Design of MRAM based logic circuits and its applications. ACM Great Lakes Symposium on VLSI 2011: 431-436 |
| c100 | | Christoph Roth, Gabriel Marchesan Almeida, Oliver Sander, Luciano Ost, Nicolas Hebert, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Jürgen Becker: Modular Framework for Multi-level Multi-device MPSoC Simulation. IPDPS Workshops 2011: 136-142 |
| c99 | | Florian Devic, Lionel Torres, Benoît Badrignans: Securing Boot of an Embedded Linux on FPGA. IPDPS Workshops 2011: 189-195 |
| c98 | | Lyonel Barthe, Luis Vitório Cargnini, Pascal Benoit, Lionel Torres: The SecretBlaze: A Configurable and Cost-Effective Open-Source Soft-Core Processor. IPDPS Workshops 2011: 310-313 |
| c97 | | Gabriel Marchesan Almeida, Rémi Busseuil, Everton Alceu Carara, Nicolas Hebert, Sameer Varyani, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Fernando Gehm Moraes: Predictive Dynamic Frequency Scaling for Multi-Processor Systems-on-Chip. ISCAS 2011: 1500-1503 |
| c96 | | Nicolas Hebert, Gabriel Marchesan Almeida, Pascal Benoit, Gilles Sassatelli, Lionel Torres: Evaluation of a distributed fault handler method for MPSoC. ISCAS 2011: 2329-2332 |
| c95 | | Gregory di Pendina, Kholdoun Torki, Guillaume Prenat, Yoann Guillemenet, Lionel Torres: Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology. PATMOS 2011: 83-91 |
| c94 | | Rémi Busseuil, Lyonel Barthe, Gabriel Marchesan Almeida, Luciano Ost, Florent Bruguier, Gilles Sassatelli, Pascal Benoit, Michel Robert, Lionel Torres: Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration. ReConFig 2011: 357-362 |
| c93 | | Weisheng Zhao, Y. Zhang, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, D. Revelosona, Claude Chappert, Lionel Torres, Luis Vitório Cargnini, R. M. Brum, Yoann Guillemenet, Gilles Sassatelli: Embedded MRAM for high-speed computing. VLSI-SoC 2011: 37-42 |
| 2010 | ||
| j15 | | Yoann Guillemenet, Lionel Torres, Gilles Sassatelli: Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories. IET Computers & Digital Techniques 4(3): 211-226 (2010) |
| j14 | | Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Nicolas Saint-Jean: Run-time mapping for dynamic reconfiguration management in embedded systems. IJES 4(3/4): 276-291 (2010) |
| j13 | | Lionel Torres, Viktor K. Prasanna: Selected Papers from ReconFig 2009 International Conference on Reconfigurable Computing and FPGAs (ReconFig 2009). Int. J. Reconfig. Comp. 2010 (2010) |
| j12 | | Imen Mansouri, Pascal Benoit, Diego Puschini, Lionel Torres, Fabien Clermidy, Gilles Sassatelli: Dynamic Energy Optimization in Network-on-Chip-Based System-on-Chips. J. Low Power Electronics 6(4): 564-577 (2010) |
| j11 | | Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez: Block-Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor-Memory Transactions. Transactions on Computational Science 10: 231-260 (2010) |
| j10 | | Benoît Badrignans, David Champagne, Reouven Elbaz, Catherine H. Gebotys, Lionel Torres: SARFUM: Security Architecture for Remote FPGA Update and Monitoring. TRETS 3(2): 8 (2010) |
| c92 | | Nicolas Hebert, Pascal Benoit, Gilles Sassatelli, Lionel Torres: D-Scale: A Scalable System-Level Dependable Method for MPSoCs. Asian Test Symposium 2010: 198-205 |
| c91 | | Jerome Di-Battista, Jean-Christophe Courrège, Bruno Rouzeyre, Lionel Torres, Philippe Perdu: When Failure Analysis Meets Side-Channel Attacks. CHES 2010: 188-202 |
| c90 | | Etienne Faure, Gabriel Marchesan Almeida, Mounir Benabdenbi, Pascal Benoit, Fabien Clermidy, François Pêcheux, Gilles Sassatelli, Lionel Torres: An in-memory monitoring database for self adaptive MP2SoCs. DASIP 2010: 97-104 |
| c89 | | Camille Jalier, Didier Lattard, Ahmed Amine Jerraya, Gilles Sassatelli, Pascal Benoit, Lionel Torres: Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem. DATE 2010: 184-189 |
| c88 | | Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres, Michel Robert: Differential Power Analysis enhancement with statistical preprocessing. DATE 2010: 1301-1304 |
| c87 |  | Lionel Torres, Yoann Guillemenet, Syed Zahid Ahmed: A Dynamic Reconfigurable MRAM based FPGA. ERSA 2010: 31-40 |
| c86 | | Lyonel Barthe, Pascal Benoit, Lionel Torres: Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures. FPL 2010: 139-144 |
| c85 | | Florian Devic, Lionel Torres, Benoît Badrignans: Secure Protocol Implementation for Remote Bitstream Update Preventing Replay Attacks on FPGA. FPL 2010: 179-182 |
| c84 | | Syed Zahid Ahmed, Gilles Sassatelli, Lionel Torres, Laurent Rouge: Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs. FPL 2010: 291-297 |
| c83 | | Camille Jalier, Didier Lattard, Gilles Sassatelli, Pascal Benoit, Lionel Torres: Flexible and distributed real-time control on a 4G telecom MPSoC. ISCAS 2010: 3961-3964 |
| c82 | | Camille Jalier, Didier Lattard, Gilles Sassatelli, Pascal Benoit, Lionel Torres: A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio. ISVLSI 2010: 345-350 |
| c81 | | Imen Mansouri, Camille Jalier, Fabien Clermidy, Pascal Benoit, Lionel Torres: Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory. ISVLSI 2010: 422-427 |
| c80 | | Victor Lomné, Philippe Maurine, Lionel Torres, Thomas Ordas, Mathieu Lisart, Jérome Toublanc: Modeling Time Domain Magnetic Emissions of ICs. PATMOS 2010: 238-249 |
| c79 | | Luis Vitório Cargnini, Yoann Guillemenet, Lionel Torres, Gilles Sassatelli: Improving the Reliability of a FPGA Using Fault-Tolerance Mechanism Based on Magnetic Memory (MRAM). ReConFig 2010: 150-155 |
| c78 | | Nicolas Hebert, Gabriel Marchesan Almeida, Pascal Benoit, Gilles Sassatelli, Lionel Torres: A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoC. ReConFig 2010: 346-351 |
| c77 | | Gabriel Marchesan Almeida, Sameer Varyani, Rémi Busseuil, Nicolas Hebert, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert: Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism. ReConFig 2010: 382-387 |
| c76 | | Gabriel Marchesan Almeida, Sameer Varyani, Rémi Busseuil, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Everton Carara, Fernando Gehm Moraes: Evaluating the impact of task migration in multi-processor systems-on-chip. SBCCI 2010: 73-78 |
| c75 | | Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres: A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks. SBCCI 2010: 115-120 |
| c74 | | Imen Mansouri, Fabien Clermidy, Pascal Benoit, Lionel Torres: A run-time distributed cooperative approach to optimize power consumption in MPSoCs. SoCC 2010: 25-30 |
| c73 | | François Poucheret, Lyonel Barthe, Pascal Benoit, Lionel Torres, Philippe Maurine, Michel Robert: Spatial EM jamming: A countermeasure against EM Analysis? VLSI-SoC 2010: 105-110 |
| 2009 | ||
| j9 | | Gabriel Marchesan Almeida, Gilles Sassatelli, Pascal Benoit, Nicolas Saint-Jean, Sameer Varyani, Lionel Torres, Michel Robert: An Adaptive Message Passing MPSoC Framework. Int. J. Reconfig. Comp. 2009 (2009) |
| j8 | | Lionel Torres, César Torres: Selected Papers from ReConFig 2008. Int. J. Reconfig. Comp. 2009 (2009) |
| j7 | | Reouven Elbaz, David Champagne, Catherine H. Gebotys, Ruby B. Lee, Nachiketh R. Potlapally, Lionel Torres: Hardware Mechanisms for Memory Authentication: A Survey of Existing Techniques and Engines. Transactions on Computational Science 4: 1-22 (2009) |
| c72 | | Syed Zahid Ahmed, Julien Eydoux, Laurent Rouge, Jean-Baptiste Cuelle, Gilles Sassatelli, Lionel Torres: Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor. DATE 2009: 184-189 |
| c71 | | Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans: Evaluation on FPGA of triple rail logic robustness against DPA and DEMA. DATE 2009: 634-639 |
| c70 | | Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres: Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC. DATE 2009: 1564-1567 |
| c69 | | Yoann Guillemenet, Syed Zahid Ahmed, Lionel Torres, Alexandre Martheley, Julien Eydoux, Jean-Baptiste Cuelle, Laurent Rouge, Gilles Sassatelli: MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs. ReConFig 2009: 18-23 |
| c68 | | Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres: Adaptive energy-aware latency-constrained DVFS policy for MPSoC. SoCC 2009: 89-92 |
| c67 | | Amine Dehbaoui, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert: Enhancing Electromagnetic Attacks Using Spectral Coherence Based Cartography. VLSI-SoC 2009: 135-155 |
| e3 | | Viktor K. Prasanna, Lionel Torres, René Cumplido (Eds.): ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings. IEEE Computer Society 2009, isbn 978-0-7695-3917-1 |
| 2008 | ||
| j6 | | Jürgen Becker, Michael Hübner, Roger Woods, Philip Heng Wai Leong, Robert Esser, Lionel Torres: Current Trends on Reconfigurable Computing. Int. J. Reconfig. Comp. 2008 (2008) |
| j5 | | Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon: On the Use of Magnetic RAMs in Field-Programmable Gate Arrays. Int. J. Reconfig. Comp. 2008 (2008) |
| j4 | | Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres: A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC. Int. J. Reconfig. Comp. 2008 (2008) |
| c66 | | Benoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli: Hierarchical Code Correction and Reliability Management in Embedded nor Flash Memories. European Test Symposium 2008: 84-90 |
| c65 | | Benoît Badrignans, Reouven Elbaz, Lionel Torres: Secure FPGA configuration architecture preventing system downgrade. FPL 2008: 317-322 |
| c64 | | Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon, Ilham Hassoune: A non-volatile run-time FPGA using thermally assisted switching MRAMS. FPL 2008: 421-426 |
| c63 | | Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres: Convergence analysis of run-time distributed optimization on adaptive systems using game theory. FPL 2008: 555-558 |
| c62 | | Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert: Bio-inspiration helps computers: A new machine. FPL 2008: 697-698 |
| c61 | | Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert: MPI-Based Adaptive Task Migration Support on the HS-Scale System. ISVLSI 2008: 105-110 |
| c60 | | Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres: Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory. ISVLSI 2008: 375-380 |
| c59 | | Thomas Ordas, Mathieu Lisart, Etienne Sicard, Philippe Maurine, Lionel Torres: Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits. PATMOS 2008: 229-236 |
| c58 | | Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres: Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoC. ReConFig 2008: 235-240 |
| c57 | | Syed Zahid Ahmed, Julien Eydoux, Michael Fernández, Laurent Rouge, Gilles Sassatelli, Lionel Torres: Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs. ReConFig 2008: 313-318 |
| c56 | | Victor Lomné, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans: Triple Rail Logic Robustness against DPA. ReConFig 2008: 415-420 |
| c55 | | David Champagne, Reouven Elbaz, Catherine H. Gebotys, Lionel Torres, Ruby B. Lee: Forward-Secure Content Distribution to Reconfigurable Hardware. ReConFig 2008: 450-455 |
| c54 | | Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert: Evaluating the robustness of secure triple track logic through prototyping. SBCCI 2008: 193-198 |
| c53 | | Benoît Badrignans, Reouven Elbaz, Lionel Torres: Secure update Mechanism for Remote Update of FPGA-Based System. SIES 2008: 221-224 |
| 2007 | ||
| c52 | | Reouven Elbaz, David Champagne, Ruby B. Lee, Lionel Torres, Gilles Sassatelli, Pierre Guillemin: TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks. CHES 2007: 289-302 |
| c51 | | Benoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli: Evaluation of design for reliability techniques in embedded flash memories. DATE 2007: 1593-1598 |
| c50 | | Benoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli: Architecture for Highly Reliable Embedded Flash Memories. DDECS 2007: 75-80 |
| c49 | | Gilles Sassatelli, Nicolas Saint-Jean, Pascal Benoit, Lionel Torres, Michel Robert, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes: Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs. FCCM 2007: 295-296 |
| c48 | | Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Fernando Moraes: A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA. IPDPS 2007: 1-8 |
| c47 | | Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert: HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems. ISVLSI 2007: 21-28 |
| c46 | | Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon: Technological hybridization for efficient runtime reconfigurable FPGAs. ISVLSI 2007: 29-34 |
| c45 | | Nicolas Saint-Jean, Camille Jalier, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert: HS Scale: A run-time adaptable MP-SoC architecture. ReCoSoC 2007: 39-46 |
| c44 | | Eduardo Wanderley Netto, Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet: IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking. ReCoSoC 2007: 138-145 |
| c43 | | Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert: Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems. ICSAMOS 2007: 88-95 |
| i1 | | Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, C. Anguille, Michel Bardouillet, Christian Buatois, Jean-Baptiste Rigaud: Hardware Engines for Bus Encryption: A Survey of Existing Techniques. CoRR abs/0710.4803 (2007) |
| 2006 | ||
| c42 | | Alex Ngouanga, Gilles Sassatelli, Lionel Torres, Thierry Gil, André Borin Suarez, Altamiro Amadeu Susin: Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform. ARC 2006: 134-145 |
| c41 | | Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez: A parallelized way to provide data encryption and integrity checking on a processor-memory bus. DAC 2006: 506-509 |
| c40 | | Alex Ngouanga, Gilles Sassatelli, Lionel Torres, André Borin Soares, Altamiro Amadeu Susin: A Contextual Resources use: a Proof of Concept through the APACHES' Platform. DDECS 2006: 44-49 |
| c39 | | Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet: PE-ICE: Parallelized Encryption and Integrity Checking Engine. DDECS 2006: 143-144 |
| c38 | | Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon: Magnetic tunnelling junction based FPGA. FPGA 2006: 123-130 |
| c37 | | Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Jean-Claude Bajard, Fernando Gehm Moraes: A Leak Resistant Architecture Against Side Channel Attacks. FPL 2006: 1-4 |
| c36 | | Nicolas Valette, Lionel Torres, Gilles Sassatelli, Frédéric Bancel: Securing embedded programmable gate arrays in secure circuits. IPDPS 2006 |
| c35 | | Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon, Jürgen Becker: Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager. ISVLSI 2006: 251-256 |
| c34 | | Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon: New non-volatile FPGA concept using Magnetic Tunneling Junction. ISVLSI 2006: 269-276 |
| c33 | | Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez: A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus. PATMOS 2006: 267-279 |
| c32 | | Nicolas Valette, Lionel Torres, Gilles Sassatelli, S. Bancel: How to Secure Embedded Programmable Gate Arrays? ReCoSoC 2006: 52-59 |
| c31 | | Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez: Efficient Combination of Data Encryption and Integrity Checking for Embedded Systems. ReCoSoC 2006: 69-75 |
| c30 | | Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon: Remanent SRAM Structure for Runtime Reconfigurable FPGA. ReCoSoC 2006: 124-130 |
| c29 | | Benoît Badrignans, Daniel Mesquita, Jean-Claude Bajard, Lionel Torres, Gilles Sassatelli, Michel Robert: A Parallel and Secure Architecture for Asymmetric Cryptography. ReCoSoC 2006: 220-224 |
| c28 | | Viktor Fischer, Lionel Torres, Daniel Mesquita: Flexible security and its technology limits. ReCoSoC 2006: 243-248 |
| e2 | | Gilles Sassatelli, Leandro Soares Indrusiak, Manfred Glesner, Lionel Torres (Eds.): Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2006, Montpellier, France, July 2006. Univ. Montpellier II 2006, isbn 2-9517461-2-1 |
| 2005 | ||
| j3 | | Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, Didier Demigny: Méthode de caractérisation des architectures d'accélérateurs flexibles pour systèmes sur puce. Technique et Science Informatiques 24(6): 725-755 (2005) |
| c27 | | Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, C. Anguille, Michel Bardouillet, Christian Buatois, Jean-Baptiste Rigaud: Hardware Engines for Bus Encryption: A Survey of Existing Techniques. DATE 2005: 40-45 |
| c26 | | Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon: Dynamic hardware multiplexing for coarse grain reconfigurable architectures. FPGA 2005: 270 |
| c25 | | Nicolas Bruchon, Gaston Cambon, Lionel Torres, Gilles Sassatelli: Magnetic remanent memory structures for dynamically reconfigurable fine grain FPGA. FPL 2005: 687-690 |
| c24 | | Pascal Benoit, Jürgen Becker, Michel Robert, Lionel Torres, Gilles Sassatelli, Gaston Cambon: Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors. FPL 2005: 703-706 |
| c23 | | Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon: Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures. IPDPS 2005 |
| c22 | | Nicolas Bruchon, Gaston Cambon, Lionel Torres, Gilles Sassatelli: Non-volatile SRAM-FPGA based on magnetic tunnelling junction. ReCoSoC 2005: 113-120 |
| c21 | | Nicolas Valette, Lionel Torres, Frédéric Bancel, Nicolas Bérard: Integration of Reconfigurable Logic on Secure Circuits. ReCoSoC 2005: 163-168 |
| c20 | | Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes: A new hardware countermeasure for masking power signatures of crypto cores. ReCoSoC 2005: 169-176 |
| c19 | | Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes: Current mask generation: a transistor level security against DPA attacks. SBCCI 2005: 115-120 |
| c18 | | Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Michel Robert, Guy Cathebras, Gilles Sassatelli, Fernando Gehm Moraes: Current Mask Generation: an Analog Circuit to Thwart DPA Attacks. VLSI-SoC 2005: 317-330 |
| e1 | | Gilles Sassatelli, Manfred Glesner, Lionel Torres, Leandro Soares Indrusiak, Thomas Hollstein (Eds.): Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2005, Montpellier, France, June 2005. Univ. Montpellier II 2005, isbn 2-9517-4611-3 |
| 2004 | ||
| j2 | | Solaiman Rahim, Bruno Rouzeyre, Lionel Torres: A Flip-Flop Matching Engine to Verify Sequential Optimizations. Computers and Artificial Intelligence 23(5): 437-460 (2004) |
| c17 | | Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon: Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability. SAMOS 2004: 128-137 |
| 2003 | ||
| c16 | | Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, Didier Demigny: A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring. FPL 2003: 722-732 |
| c15 | | Solaiman Rahim, Bruno Rouzeyre, Lionel Torres, Jérôme Rampon: Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking. HLDVT 2003: 129-134 |
| c14 | | Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon: Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability. IPDPS 2003: 176 |
| c13 | | Daniel Mesquita, Lionel Torres, Fernando Gehm Moraes, Gilles Sassatelli, Michel Robert: Are coarse grain reconfigurable architectures suitable for cryptography? VLSI-SOC 2003: 276-281 |
| 2002 | ||
| c12 | | Gilles Sassatelli, Lionel Torres, Pascal Benoit, Thierry Gil, Camille Diou, Gaston Cambon, Jérôme Galy: Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications. DATE 2002: 553-558 |
| c11 | | Christel-Loic Tisse, Lionel Martin, Lionel Torres, Michel Robert: Iris recognition system for person identification. PRIS 2002: 186-199 |
| 2001 | ||
| c10 | | Camille Diou, Lionel Torres, Michel Robert: An embedded core for the 2D wavelet transform. ETFA (2) 2001: 179-186 |
| c9 | | Gilles Sassatelli, Lionel Torres, Jérôme Galy, Gaston Cambon, Camille Diou: The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems. FPL 2001: 409-419 |
| c8 | | Gilles Sassatelli, Lionel Torres, Pascal Benoit, Gaston Cambon, Michel Robert, Jérôme Galy: Dynamically Reconfigurable Architectures for Digital Signal Processing Applications. VLSI-SOC 2001: 63-74 |
| c7 | | Gilles Sassatelli, Gaston Cambon, Jérôme Galy, Lionel Torres: A Dynamically Reconfigurable Architecture for Embedded Systems. IEEE International Workshop on Rapid System Prototyping 2001: 32-37 |
| 2000 | ||
| c6 | | |
| 1999 | ||
| c5 | | Camille Diou, Lionel Torres, Michel Robert: Implementation of a Wavelet Transform Architecture for Image Processing. VLSI 1999: 101-112 |
| c4 | | S. Raimbault, Gilles Sassatelli, Gamille Cambon, Michel Robert, Sébastien Pillement, Lionel Torres: Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies. VLSI 1999: 407-414 |
| c3 | | Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon: Fast Prototyping: A Case Study - The JPEG Compression Algorithm. IEEE International Workshop on Rapid System Prototyping 1999: 87- |
| 1998 | ||
| j1 | | Lionel Torres, El-Bay Bourennane, Michel Robert, Michel Paindavoine: A Recursive Digital Filter Implementation for Noisy and Blurred Images. Real-Time Imaging 4(3): 181-191 (1998) |
| 1996 | ||
| c2 | | Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon: Concurrent Design of Hardware/Software Dedicated Systems. FPL 1996: 410-414 |
| 1994 | ||
| c1 | | Michel Robert, Lionel Torres, Fernando Moraes, Daniel Auvergne: Influence of Locig Block Layout Architecture on FPGA Performance. FPL 1994: 34-44 |
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