Cesar Torres-Huitzil

Marco Delgadillo-Escobar, Cesar Torres-Huitzil: FPGA implementation of Pseudorandom Number Generators with a generic 2-D cellular automata architecture. CONIELECOMP 2012: 138-143

Lorenzo Antonio Delgado-Guillen, Jose Juan Garcia-Hernandez, Cesar Torres-Huitzil: Validating the existence of watermarks on digital images using a mobile phone. ICITST 2012: 51-55

Horacio Rostro-González, Guillaume Garreau, Andreas G. Andreou, Julius Georgiou, Jose Hugo Barron-Zambrano, Cesar Torres-Huitzil: An FPGA-based approach for parameter estimation in spiking neural networks. ISCAS 2012: 2897-2900

Marco Aurelio Nuño-Maganda, Miguel Arias-Estrada, Cesar Torres-Huitzil, Héctor Hugo Avilés-Arriaga, Yahir Hernandez-Mier, Miguel Morales-Sandoval: A Hardware Architecture for Image Clustering Using Spiking Neural Networks. ISVLSI 2012: 261-266

Jose Hugo Barron-Zambrano, Cesar Torres-Huitzil, Horacio Rostro-González: Versatile FPGA-based locomotion platform for legged robots. ReConFig 2012: 1-6

Jose Hugo Barron-Zambrano, Cesar Torres-Huitzil: Two-phase GA parameter tunning method of CPGs for quadruped gaits. IJCNN 2011: 1767-1774

Roberto Perez-Andrade, Cesar Torres-Huitzil, René Cumplido, Juan M. Campos: On a Hybrid and General Control Scheme for Algorithms Represented as a Polytope. IPDPS Workshops 2011: 330-333

Jose Hugo Barron-Zambrano, Cesar Torres-Huitzil, Jose Juan Garcia-Hernandez: FPGA-based CPG Robot Locomotion Modulation Using a Fuzzy Scheme and Visual Information. ReConFig 2011: 291-296

Marco Aurelio Nuño-Maganda, Cesar Torres-Huitzil: A temporal coding hardware implementation for spiking neural networks. SIGARCH Computer Architecture News 38(4): 2-7 (2010)

Jose Hugo Barron-Zambrano, Cesar Torres-Huitzil, Bernard Girau: Hardware Implementation of a CPG-Based Locomotion Control for Quadruped Robots. ICANN (2) 2010: 276-285

Bernard Girau, Cesar Torres-Huitzil, Nikolaos Vlassopoulos, Jose Hugo Barron-Zambrano: Reaction Diffusion and Chemotaxis for Decentralized Gathering on FPGAs. Int. J. Reconfig. Comp. 2009 (2009)

Marco Aurelio Nuño-Maganda, Miguel Arias-Estrada, Cesar Torres-Huitzil, Bernard Girau: Hardware implementation of Spiking Neural Network classifiers based on backpropagation-based learning algorithms. IJCNN 2009: 2294-2301

Cesar Torres-Huitzil: On the Implementation of Central Pattern Generators for Periodic Rhythmic Locomotion. ReConFig 2009: 422-426

Cesar Torres-Huitzil, Bernard Girau: Implementation of Central Pattern Generator in an FPGA-Based Embedded System. ICANN (2) 2008: 179-187

Cesar Torres-Huitzil, Bernard Girau, Miguel Arias-Estrada: Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity. ICANN (2) 2008: 188-197

Cesar Torres-Huitzil, Bernard Girau, Amine M. Boumaza, Bruno Scherrer: Embedded Harmonic Control for Trajectory Planning in Large Environments. ReConFig 2008: 7-12

Jose Hugo Barron-Zambrano, Cesar Torres-Huitzil, Mauricio Cerda: Flexible Architecture for Three Classes of Optical Flow Extraction Algorithms. ReConFig 2008: 13-18

Bernard Girau, Cesar Torres-Huitzil: Fast Implementation of a Bio-inspired Model for Decentralized Gathering. ReConFig 2008: 229-234

Bernard Girau, Cesar Torres-Huitzil: Massively distributed digital implementation of an integrate-and-fire LEGION network for visual scene segmentation. Neurocomputing 70(7-9): 1186-1197 (2007)

Cesar Torres-Huitzil, Bernard Girau, Adrien Gauffriau: Hardware/Software Codesign for Embedded Implementation of Neural Networks. ARC 2007: 167-178

Marco Aurelio Nuño-Maganda, Miguel Arias-Estrada, Cesar Torres-Huitzil: High Performance Hardware Implementation of SpikeProp Learning: Potential and Tradeoffs. FPT 2007: 129-136

Bernard Girau, Cesar Torres-Huitzil: FPGA implementation of an integrate-and-fire LEGION model for image segmentation. ESANN 2006: 173-178

Cesar Torres-Huitzil: Area-Efficient Implementation of a Pulse-Mode Neuron Model. FPL 2006: 1-4

Cesar Torres-Huitzil: A Bit-Stream Pulse-Based Digital Neuron Model for Neural Networks. ICONIP (3) 2006: 1150-1159

René Cumplido-Parra, Cesar Torres-Huitzil, Andrés D. García (Eds.): 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006, San Luis Potosi, Mexico, September 20-22, 2006. IEEE Computer Society 2006, isbn 1-4244-0690-0

Cesar Torres-Huitzil, Miguel Arias-Estrada: FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing. EURASIP J. Adv. Sig. Proc. 2005(7): 1024-1034 (2005)

Cesar Torres-Huitzil, Bernard Girau, Claudio Castellanos Sánchez: On-chip visual perception of motion: A bio-inspired connectionist model on FPGA. Neural Networks 18(5-6): 557-565 (2005)

Cesar Torres-Huitzil, Bernard Girau: FPGA Implementation of an Excitatory and Inhibitory Connectionist Model for Motion Perception. FPT 2005: 259-266

Cesar Torres-Huitzil, Miguel Arias-Estrada: Real-time image processing with a compact FPGA-based systolic architecture. Real-Time Imaging 10(3): 177-187 (2004)

Santos López-Estrada, René Cumplido-Parra, Cesar Torres-Huitzil: A Hybrid Approach for Target Detection Using CFAR Algorithm and Image Processing. ENC 2004: 108-115

Cesar Torres-Huitzil, René Cumplido-Parra, Santos López-Estrada: Design and Implementation of a CFAR Processor for Target Detection. FPL 2004: 943-947

Cesar Torres-Huitzil, Miguel Arias-Estrada: Configurable Hardware Architecture for Real-Time Window-Based Image Processing. FPL 2003: 1008-1011

Cesar Torres-Huitzil, Selene Maya-Rueda, Miguel Arias-Estrada: A reconfigurable vision system for real-time applications. FPT 2002: 286-289

Miguel Arias-Estrada, Cesar Torres-Huitzil: Real-time field programmable gate array architecture for computer vision. J. Electronic Imaging 10(1): 289-296 (2001)

Cesar Torres-Huitzil, Miguel Arias-Estrada: An FPGA Architecture for High Speed Edge and Corner Detection. CAMP 2000: 112-116

Selene Maya, Rocio Reynoso, Cesar Torres-Huitzil, Miguel Arias-Estrada: Compact Spiking Neural Network Implementation in FPGA. FPL 2000: 270-276