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Nur A. Touba
2010 – today
- 2013
[j28]Joon-Sung Yang, Nur A. Touba: Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug. IEEE Trans. VLSI Syst. 21(2): 320-328 (2013)- 2012
- [j27]Joon-Sung Yang, Nur A. Touba, Benoit Nadeau-Dostie: Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops. IEEE Trans. Computers 61(10): 1473-1483 (2012)
- [j26]Joon-Sung Yang, Nur A. Touba: Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 31(3): 442-446 (2012)
- [j25]Joon-Sung Yang, Nur A. Touba: X-Canceling MISR Architectures for Output Response Compaction With Unknown Values. IEEE Trans. on CAD of Integrated Circuits and Systems 31(9): 1417-1427 (2012)
- [c94]Asad Amin Bawa, Muhammad Tauseef Rab, Nur A. Touba: Using partial masking in X-chains to increase output compaction for an X-canceling MISR. DFT 2012: 19-24
- [c93]Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba: Implementing defect tolerance in 3D-ICs by exploiting degrees of freedom in assembly. DFT 2012: 178-181
- [c92]Sreenivaas S. Muthyala, Nur A. Touba: Improving test compression by retaining non-pivot free variables in sequential linear decompressors. ITC 2012: 1-7
- [c91]Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba: Using asymmetric layer repair capability to reduce the cost of yield enhancement in 3D stacked memories. VLSI-SoC 2012: 195-200
- [c90]Jinsuk Chung, Nur A. Touba: Exploiting X-correlation in output compression via superset X-canceling. VTS 2012: 182-187
- 2011
- [c89]Rudrajit Datta, Nur A. Touba: X-Stacking - A Method for Reducing Control Data for Output Compaction. DFT 2011: 332-338
- [c88]Rudrajit Datta, Nur A. Touba: Generating Burst-Error Correcting Codes from Orthogonal Latin Square Codes - A Graph Theoretic Approach. DFT 2011: 367-373
- [c87]Rudrajit Datta, Nur A. Touba: Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories. VTS 2011: 134-139
- 2010
- [j24]Jinkyu Lee, Nur A. Touba: Correlation-Based Rectangular Encoding. IEEE Trans. VLSI Syst. 18(10): 1483-1492 (2010)
- [c86]Rudrajit Datta, Nur A. Touba: Post-manufacturing ECC customization based on Orthogonal Latin Square codes and its application to ultra-low power caches. ITC 2010: 212-218
- [c85]Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li: CSER: BISER-based concurrent soft-error resilience. VTS 2010: 153-158
2000 – 2009
- 2009
- [c84]Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba: Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points. DFT 2009: 20-28
- [c83]Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba: Improving Memory Repair by Selective Row Partitioning. DFT 2009: 211-219
- [c82]Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba: Test point insertion using functional flip-flops to drive control points. ITC 2009: 1-10
- [c81]Joon-Sung Yang, Nur A. Touba, Shih-Yu Yang, T. M. Mak: An industrial case study for X-canceling MISR. ITC 2009: 1-10
- [c80]Rudrajit Datta, Nur A. Touba: Exploiting Unused Spare Columns to Improve Memory ECC. VTS 2009: 47-52
- [c79]Joon-Sung Yang, Nur A. Touba: Automated Selection of Signals to Observe for Efficient Silicon Debug. VTS 2009: 79-84
- 2008
- [j23]Scott Davidson, Nur A. Touba: Guest Editors' Introduction: Progress in Test Compression. IEEE Design & Test of Computers 25(2): 112-113 (2008)
- [j22]
- [j21]Nur A. Touba, Adelio Salsano, Minsu Choi: Guest Editorial. J. Electronic Testing 24(1-3): 9-10 (2008)
- [c78]
- [c77]Ritesh Garg, Richard Putman, Nur A. Touba: Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation. VTS 2008: 35-42
- [c76]Joon-Sung Yang, Nur A. Touba: Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. VTS 2008: 345-351
- [e2]Douglas Young, Nur A. Touba (Eds.): 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008. IEEE 2008, ISBN 978-1-4244-2403-0
- 2007
- [j20]Kedarnath J. Balakrishnan, Nur A. Touba: Relationship Between Entropy and Test Data Compression. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 386-395 (2007)
- [j19]Jinkyu Lee, Nur A. Touba: LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 396-401 (2007)
- [c75]Avijit Dutta, Nur A. Touba: Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code. DFT 2007: 3-11
- [c74]Nur A. Touba: X-canceling MISR - An X-tolerant methodology for compacting output responses with unknowns using a MISR. ITC 2007: 1-10
- [c73]Richard Putman, Nur A. Touba: Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression. VTS 2007: 211-218
- [c72]Avijit Dutta, Nur A. Touba: Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code. VTS 2007: 349-354
- [e1]Cristiana Bolchini, Yong-Bin Kim, Adelio Salsano, Nur A. Touba (Eds.): 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy. IEEE Computer Society 2007, ISBN 0-7695-2885-6
- 2006
- [j18]Nur A. Touba: Survey of Test Vector Compression Techniques. IEEE Design & Test of Computers 23(4): 294-303 (2006)
- [j17]Eric MacDonald, Nur A. Touba: Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits. IEEE Trans. VLSI Syst. 14(6): 587-595 (2006)
- [j16]Kedarnath J. Balakrishnan, Nur A. Touba: Improving Linear Test Data Compression. IEEE Trans. VLSI Syst. 14(11): 1227-1237 (2006)
- [c71]Avijit Dutta, Nur A. Touba: Synthesis of Efficient Linear Test Pattern Generators. DFT 2006: 206-214
- [c70]Avijit Dutta, Nur A. Touba: Using Limited Dependence Sequential Expansion for Decompressing Test Vectors. ITC 2006: 1-9
- [c69]
- [c68]Jinkyu Lee, Nur A. Touba: Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding. VTS 2006: 252-257
- 2005
- [j15]Shalini Ghosh, Sugato Basu, Nur A. Touba: Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits. J. Low Power Electronics 1(1): 63-72 (2005)
- [c67]Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil: Compressing Functional Tests for Microprocessors. Asian Test Symposium 2005: 428-433
- [c66]Kedarnath J. Balakrishnan, Nur A. Touba: Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination. DATE 2005: 1130-1135
- [c65]
- [c64]Samuel I. Ward, Chris Schattauer, Nur A. Touba: Using Statistical Transformations to Improve Compression for Linear Decompressors. DFT 2005: 42-50
- [c63]Avijit Dutta, Terence Rodrigues, Nur A. Touba: Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier. ISVLSI 2005: 200-205
- [c62]
- [c61]Avijit Dutta, Nur A. Touba: Synthesis of nonintrusive concurrent error detection using an even error detecting function. ITC 2005: 8
- [c60]Shalini Ghosh, Sugato Basu, Nur A. Touba: Synthesis of Low Power CED Circuits Based on Parity Codes. VTS 2005: 315-320
- 2004
- [j14]Kedarnath J. Balakrishnan, Nur A. Touba: Matrix-based software test data decompression for systems-on-a-chip. Journal of Systems Architecture 50(5): 247-256 (2004)
- [j13]C. V. Krishna, Abhijit Jas, Nur A. Touba: Achieving high encoding efficiency with partial dynamic LFSR reseeding. ACM Trans. Design Autom. Electr. Syst. 9(4): 500-516 (2004)
- [j12]Abhijit Jas, Bahram Pouya, Nur A. Touba: Test data compression technique for embedded cores using virtual scan chains. IEEE Trans. VLSI Syst. 12(7): 775-781 (2004)
- [j11]Kartik Mohanram, Nur A. Touba: Lowering power consumption in concurrent checkers via input ordering. IEEE Trans. VLSI Syst. 12(11): 1234-1243 (2004)
- [j10]Abhijit Jas, C. V. Krishna, Nur A. Touba: Weighted pseudorandom hybrid BIST. IEEE Trans. VLSI Syst. 12(12): 1277-1283 (2004)
- [c59]Shalini Ghosh, Eric MacDonald, Sugato Basu, Nur A. Touba: Low-power weighted pseudo-random BIST using special scan cells. ACM Great Lakes Symposium on VLSI 2004: 86-91
- [c58]Jinkyu Lee, Nur A. Touba: Low Power Test Data Compression Based on LFSR Reseeding. ICCD 2004: 180-185
- [c57]Kedarnath J. Balakrishnan, Nur A. Touba: Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion. ITC 2004: 936-944
- [c56]Shalini Ghosh, Nur A. Touba, Sugato Basu: Reducing Power Consumption in Memory ECC Checkers. ITC 2004: 1322-1331
- [c55]C. V. Krishna, Nur A. Touba: 3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme. VTS 2004: 79-86
- 2003
- [j9]Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba: An efficient test vector compression scheme using selective Huffman coding. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 797-806 (2003)
- [j8]Lei Li, Krishnendu Chakrabarty, Nur A. Touba: Test data compression using dictionaries with selective entries and fixed-length indices. ACM Trans. Design Autom. Electr. Syst. 8(4): 470-490 (2003)
- [c54]Kedarnath J. Balakrishnan, Nur A. Touba: Scan-Based BIST Diagnosis Using an Embedded Processor. DFT 2003: 209-216
- [c53]
- [c52]Kartik Mohanram, Nur A. Touba: Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. DFT 2003: 433-
- [c51]C. V. Krishna, Nur A. Touba: Adjustable Width Linear Combinational Scan Vector Decompression. ICCAD 2003: 863-866
- [c50]Kartik Mohanram, Egor S. Sogomonyan, Michael Gössel, Nur A. Touba: Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits. IOLTS 2003: 35-
- [c49]Shalini Ghosh, Sugato Basu, Nur A. Touba: Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering. ISVLSI 2003: 246-249
- [c48]Kartik Mohanram, Nur A. Touba: Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. ITC 2003: 893-901
- [c47]Kartik Mohanram, Nur A. Touba: Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. VTS 2003: 121-127
- [c46]Kedarnath J. Balakrishnan, Nur A. Touba: Deterministic Test Vector Decompression in Software Using Linear Operations. VTS 2003: 225-231
- 2002
- [j7]Abhijit Jas, Nur A. Touba: Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor. J. Electronic Testing 18(4-5): 503-514 (2002)
- [j6]
- [c45]Ranganathan Sankaralingam, Nur A. Touba: Reducing Test Power During Test Using Programmable Scan Chain Disable. DELTA 2002: 159-166
- [c44]Kartik Mohanram, Nur A. Touba: Input Ordering in Concurrent Checkers to Reduce Power Consumption. DFT 2002: 87-98
- [c43]Ranganathan Sankaralingam, Nur A. Touba: Inserting Test Points to Control Peak Power During Scan Testing. DFT 2002: 138-146
- [c42]Kedarnath J. Balakrishnan, Nur A. Touba: Matrix-Based Test Vector Decompression Using an Embedded Processor. DFT 2002: 159-165
- [c41]Kartik Mohanram, C. V. Krishna, Nur A. Touba: A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL. ISCAS (1) 2002: 577-580
- [c40]C. V. Krishna, Nur A. Touba: Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression. ITC 2002: 321-330
- [c39]
- [c38]Ranganathan Sankaralingam, Nur A. Touba: Controlling Peak Power During Scan Testing. VTS 2002: 153-159
- 2001
- [j5]Nur A. Touba, Edward J. McCluskey: Bit-fixing in pseudorandom sequences for scan BIST. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 545-555 (2001)
- [c37]Jayabrata Ghosh-Dastidar, Nur A. Touba: Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability. DFT 2001: 215-220
- [c36]C. V. Krishna, Abhijit Jas, Nur A. Touba: Test vector encoding using partial LFSR reseeding. ITC 2001: 885-893
- [c35]Abhijit Jas, C. V. Krishna, Nur A. Touba: Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme. VTS 2001: 2-8
- [c34]Ranganathan Sankaralingam, Nur A. Touba, Bahram Pouya: Reducing Power Dissipation during Test Using Scan Chain Disable. VTS 2001: 319-325
- 2000
- [c33]Eric MacDonald, Nur A. Touba: Testing domino circuits in SOI technology. Asian Test Symposium 2000: 441-446
- [c32]Debaleena Das, Nur A. Touba, Markus Seuring, Michael Gössel: Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes. IOLTW 2000: 171-
- [c31]Debaleena Das, Nur A. Touba: Reducing test data volume using external/LBIST hybrid test patterns. ITC 2000: 115-122
- [c30]Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba: Static Compaction Techniques to Control Scan Vector Power Dissipation. VTS 2000: 35-42
- [c29]Abhijit Jas, Bahram Pouya, Nur A. Touba: Virtual Scan Chains: A Means for Reducing Scan Length in Cores. VTS 2000: 73-78
- [c28]Jayabrata Ghosh-Dastidar, Nur A. Touba: A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains. VTS 2000: 79-88
1990 – 1999
- 1999
- [j4]Debaleena Das, Nur A. Touba: Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes. J. Electronic Testing 15(1-2): 145-155 (1999)
- [j3]Nur A. Touba, Edward J. McCluskey: RP-SYN: synthesis of random pattern testable circuits with test point insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 18(8): 1202-1213 (1999)
- [c27]Abhijit Jas, Kartik Mohanram, Nur A. Touba: An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. Asian Test Symposium 1999: 275-
- [c26]Abhijit Jas, Nur A. Touba: Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. ICCD 1999: 418-
- [c25]W. Quddus, Abhijit Jas, Nur A. Touba: Configuration self-test in FPGA-based reconfigurable systems. ISCAS (1) 1999: 97-100
- [c24]P. K. Jaini, Nur A. Touba: Observing test response of embedded cores through surrounding logic. ISCAS (1) 1999: 119-123
- [c23]Jayabrata Ghosh-Dastidar, Debaleena Das, Nur A. Touba: Fault diagnosis in scan-based BIST using both time and space information. ITC 1999: 95-102
- [c22]Eric MacDonald, Nur A. Touba: Delay testing of SOI circuits: Challenges with the history effect. ITC 1999: 269-275
- [c21]Debaleena Das, Nur A. Touba: A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems. VLSI Design 1999: 266-269
- [c20]Abhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba: Scan Vector Compression/Decompression Using Statistical Coding. VTS 1999: 114-120
- [c19]Jayabrata Ghosh-Dastidar, Nur A. Touba: Adaptive Techniques for Improving Delay Fault Diagnosis. VTS 1999: 168-172
- [c18]Debaleena Das, Nur A. Touba: Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits. VTS 1999: 370-377
- 1998
- [c17]Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunderlich: Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST. Asian Test Symposium 1998: 492-499
- [c16]Jayabrata Ghosh-Dastidar, Nur A. Touba: A Systematic Approach for Diagnosing Multiple Delay Faults. DFT 1998: 211-216
- [c15]Zhe Zhao, Bahram Pouya, Nur A. Touba: BETSY: synthesizing circuits for a specified BIST environment. ITC 1998: 144-153
- [c14]Abhijit Jas, Nur A. Touba: Test vector decompression via cyclical scan chains and its application to testing core-based designs. ITC 1998: 458-464
- [c13]Bahram Pouya, Nur A. Touba: Synthesis of Zero-Aliasing Elementary-Tree Space Compactors. VTS 1998: 70-77
- [c12]Debaleena Das, Nur A. Touba: Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes. VTS 1998: 309-317
- 1997
- [j2]Nur A. Touba, Bahram Pouya: Using Partial Isolation Rings to Test Core-Based Designs. IEEE Design & Test of Computers 14(4): 52-59 (1997)
- [j1]Nur A. Touba, Edward J. McCluskey: Logic synthesis of multilevel circuits with concurrent error detection. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 783-789 (1997)
- [c11]Nur A. Touba, Edward J. McCluskey: Pseudo-Random Pattern Testing of Bridging Faults. ICCD 1997: 54-60
- [c10]Bahram Pouya, Nur A. Touba: Modifying User-Defined Logic for Test Access to Embedded Cores. ITC 1997: 60-68
- [c9]
- [c8]Nur A. Touba: Obtaining High Fault Coverage with Circular BIST Via State Skipping. VTS 1997: 410-415
- 1996
- [c7]Nur A. Touba, Edward J. McCluskey: Altering a Pseudo-Random Bit Sequence for Scan-Based BIST. ITC 1996: 167-175
- [c6]
- [c5]
- 1995
- [c4]Nur A. Touba, Edward J. McCluskey: Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST. ITC 1995: 674-682
- [c3]
- 1994
- [c2]Nur A. Touba, Edward J. McCluskey: Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. ICCAD 1994: 651-654
- [c1]Nur A. Touba, Edward J. McCluskey: Automated Logic Synthesis of Random-Pattern-Testable Circuits. ITC 1994: 174-183
Coauthor Index
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last updated on 2013-01-24 21:44 CET by the dblp team