Chia-Chun Tsai

Chia-Chun Tsai, Chung-Chieh Kuo, Feng-Tzu Hsu, Trong-Yen Lee: Discharge-path-based antenna effect detection and fixing for X-architecture clock tree. Integration 45(1): 76-90 (2012)

Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho, Chia-Chun Tsai: Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs. ACM Trans. Design Autom. Electr. Syst. 17(3): 34 (2012)

Chia-Chun Tsai, Tsung-Ming Liu, Trong-Yen Lee: Micro fuel cell power management circuit design for portable devices. FSKD 2012: 2493-2496

Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee: Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement. IEICE Transactions 94-A(2): 706-716 (2011)

Chung-Chieh Kuo, Chia-Chun Tsai, Trong-Yen Lee: Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration. Integration 44(1): 87-101 (2011)

Chia-Chun Tsai, Sheng-Bin Dai, Trong-Yen Lee: The RF Circuit Design of Power and Data Contactless Transmission for ISO/IEC 14443-2 Type B. Journal of Circuits, Systems, and Computers 20(8): 1637-1658 (2011)

Trong-Yen Lee, Che-Cheng Hu, Li-Wen Lai, Chia-Chun Tsai: Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems. J. Inf. Sci. Eng. 26(4): 1289-1305 (2010)

Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee: Double-via insertion enhanced X-architecture clock routing for reliability. ISCAS 2010: 3413-3416

Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee: Antenna Violation Avoidance/Fixing for X-clock routing. ISQED 2010: 508-514

Chia-Chun Tsai, Kai-Wei Hong, Trong-Yen Lee: A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital converters. Journal of Circuits, Systems, and Computers 18(5): 933-945 (2009)

Chia-Chun Tsai, Chin-Yen Lin, Yuh-Shyan Hwang, Trong-Yen Lee: The Design of a Li-ion Battery Charger Based on Multimode LDO Technology. Journal of Circuits, Systems, and Computers 18(5): 947-963 (2009)

Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee: GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay. IEICE Transactions 91-A(1): 365-374 (2008)

Chia-Chun Tsai, Wei-Shi Lin, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee: Layer assignment considering manufacturability in X-architecture clock tree. CIT 2008: 880-885

Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao: X-clock routing based on pattern matching. SoCC 2008: 357-360

Jan-Ou Wu, Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee: Zero-Skew Driven Buffered RLC Clock Tree Construction. IEICE Transactions 90-A(3): 651-658 (2007)

Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao: Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems. IIH-MSP 2007: 19-22

Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao: An Efficiently Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems. IMECS 2007: 346-351

Chia-Chun Tsai, Hann-Cheng Huang, Trong-Yen Lee, Wen-Ta Lee, Jan-Ou Wu: Using Stack Reconstruction on RTL Orthogonal Scan Chain Design. J. Inf. Sci. Eng. 22(6): 1585-1599 (2006)

Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee: Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction. APCCAS 2006: 812-815

Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao: Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion. APCCAS 2006: 1285-1288

Trong-Yen Lee, Yang-Hsin Fan, Chia-Chun Tsai: Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion. ICICIC (2) 2006: 515-518

Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai: Inductance extraction for general interconnect structures. ISCAS 2006

Chia-Chun Tsai, Huang-Chi Chou, Trong-Yen Lee, Rong-Shue Hsiao: A single chip image sensor embedded smooth spatial filter with A/D conversion. ISCAS 2006

Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao: Coupling aware RLC-based clock routings for crosstalk minimization. ISCAS 2006

Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee: Zero-Skew Driven for RLC Clock Tree Construction in SoC. ICITA (1) 2005: 561-566

Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang: A new low-power turbo decoder using HDA-DHDD stopping iteration. ISCAS (2) 2005: 1040-1043

Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen: A new CCII-based pipelined analog to digital converter. ISCAS (6) 2005: 6170-6173

Pei-Yung Hsiao, Yu-Chun Hsu, Wen-Ta Lee, Chia-Chun Tsai, Chia-Hao Lee: An embedded analog spatial filter design of the current-mode CMOS image sensor. IEEE Trans. Consumer Electronics 50(3): 945-951 (2004)

Trong-Yen Lee, Yang-Hsin Fan, Tsung-Hsun Yang, Chia-Chun Tsai, Wen-Ta Lee, Yuh-Shyan Hwang: RCGES: Retargetable Code Generation for Embedded Systems. ATVA 2004: 415-425

Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai: Efficient routability check algorithms for segmented channel routing. ACM Trans. Design Autom. Electr. Syst. 5(3): 735-747 (2000)

Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho: An Efficient Two-Level Partitioning Algorithm for VLSI Circuits. ASP-DAC 1999: 69-72

Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai: An Automatic Router for the Pin Grid Array Package. ASP-DAC 1999: 133-136

Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai: An Even Wiring Approach to the Ball Grid Array Package Routing. ICCD 1999: 303-306

Chia-Chun Tsai, Chwan-Ming Wang, Sao-Jie Chen: NEWS: a net-even-wiring system for the routing on a multilayer PGA package. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 182-189 (1998)

Cheng-Hsing Yang, Chia-Chun Tsai, Jan-Ming Ho, Sao-Jie Chen: Hmap: a fast mapper for EPGAs using extended GBDD hash tables. ACM Trans. Design Autom. Electr. Syst. 2(2): 135-150 (1997)

Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng: Performance driven bus buffer insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 15(4): 429-437 (1996)

Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin: Performance driven multiple-source bus synthesis using buffer insertion. ASP-DAC 1995

Chia-Chun Tsai, Sao-Jie Chen: A Linear Time Algorithm for Planar Moat Routing. J. Inf. Sci. Eng. 10(1): 111-127 (1994)

Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng: An H-V alternating router. IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 976-991 (1992)

Pei-Yung Hsiao, S. F. Steven Chen, Chia-Chun Tsai, Wu-Shiung Feng: A knowledge-based program for compacting mask layout of integrated circuits. Computer-Aided Design 23(3): 223-231 (1991)

Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng: Generalized terminal connectivity problem for multilayer layout scheme. Computer-Aided Design 22(7): 423-433 (1990)

Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng: An H-V Tile-Expansion Router. J. Inf. Sci. Eng. 6(3): 173-189 (1990)