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Kun-Han Tsai
2010 – today
- 2013
[j6]Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai: Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 32(5): 737-747 (2013)- 2012
- [c28]Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng: Programmable Leakage Test and Binning for TSVs. Asian Test Symposium 2012: 43-48
- [c27]Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai: Small delay testing for TSVs in 3-D ICs. DAC 2012: 1031-1036
- [c26]Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter: A unified method for parametric fault characterization of post-bond TSVs. ITC 2012: 1-10
- 2010
- [c25]Meng-Fan Wu, Hsin-Cheih Pan, T.-H. Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng: Improved weight assignment for logic switching activity during at-speed test pattern generation. ASP-DAC 2010: 493-498
- [c24]Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, Ken Amstutz: Scan based speed-path debug for a microprocessor. European Test Symposium 2010: 207-212
- [c23]Chih-Peng Li, Sen-Hung Wang, Kun-Han Tsai: A Low Complexity Transmitter Architecture and Its Application to PAPR Reduction in SFBC MIMO-OFDM Systems. ICC 2010: 1-5
- [c22]Meng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli: A scalable quantitative measure of IR-drop effects for scan pattern generation. ICCAD 2010: 162-167
- [c21]Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Augusli Kifli: Test cycle power optimization for scan-based designs. ITC 2010: 134-143
2000 – 2009
- 2009
- [j5]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Timing-Aware Multiple-Delay-Fault Diagnosis. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 245-258 (2009)
- [c20]Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng: At-Speed Scan Test Method for the Timing Optimization and Calibration. Asian Test Symposium 2009: 430-433
- [c19]Ruifeng Guo, Wu-Tung Cheng, Kun-Han Tsai: Speed-Path Debug Using At-Speed Scan Test Patterns. European Test Symposium 2009: 11-16
- 2008
- [j4]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Improving the Resolution of Single-Delay-Fault Diagnosis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 932-945 (2008)
- [c18]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Timing-Aware Multiple-Delay-Fault Diagnosis. ISQED 2008: 246-253
- 2007
- [c17]Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski: Test Generation in the Presence of Timing Exceptions and Constraints. DAC 2007: 688-693
- [c16]Teresa L. McLaurin, Rich Slobodnik, Kun-Han Tsai, Ana Keim: Enhanced testing of clock faults. ITC 2007: 1-9
- 2006
- [j3]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Analysis and methodology for multiple-fault diagnosis. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 558-575 (2006)
- [c15]Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski: Delay Fault Diagnosis for Non-Robust Test. ISQED 2006: 463-472
- [c14]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. ITC 2006: 1-10
- [c13]Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich: Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis. ITC 2006: 1-9
- [c12]Vlado Vorisek, Bruce Swanson, Kun-Han Tsai, Dhiraj Goswami: Improved Handling of False and Multicycle Paths in ATPG. VTS 2006: 160-165
- 2005
- [j2]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Delay-fault diagnosis using timing information. IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1315-1325 (2005)
- [c11]
- 2004
- [c10]Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski: Compactor Independent Direct Diagnosis. Asian Test Symposium 2004: 204-209
- [c9]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Diagnosis of Hold Time Defects. ICCD 2004: 192-199
- [c8]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Delay Fault Diagnosis Using Timing Information. ISQED 2004: 485-490
- [c7]Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski: Realizing High Test Quality Goals with Smart Test Resource Usage. ITC 2004: 525-533
- 2003
- [c6]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Multiple Fault Diagnosis Using n-Detection Tests. ICCD 2003: 198-
- [c5]Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski: An Efficient and Effective Methodology on the Multiple Fault Diagnosis. ITC 2003: 329-338
- [c4]Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski: Impact of Multiple-Detect Test Patterns on Product Quality. ITC 2003: 1031-1040
- 2002
- [c3]Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian: Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC 2002: 301-310
- 2000
- [j1]Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska: Star test: the theory and its applications. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1052-1064 (2000)
1990 – 1999
- 1997
- [c2]Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska: STARBIST: Scan Autocorrelated Random Pattern Generation. DAC 1997: 472-477
- [c1]Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski: Scan-Encoded Test Pattern Generation for BIST. ITC 1997: 548-556
Coauthor Index
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last updated on 2013-05-25 21:21 CEST by the dblp team