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Chi-Ying Tsui
2010 – today
- 2013
[c84]Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu: SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model. DATE 2013: 354-357- [c83]Yan Lu, Xing Li, Wing-Hung Ki, Chi-Ying Tsui, C. Patrick Yue: A 13.56MHz fully integrated 1X/2X active rectifier with compensated bias current for inductively powered devices. ISSCC 2013: 66-67
- 2012
- [c82]Zhiliang Qian, Paul Bogdan, Guopeng Wei, Chi-Ying Tsui, Radu Marculescu: A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture. CODES+ISSS 2012: 161-170
- [c81]Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui: A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels. DATE 2012: 1295-1300
- [c80]YouZhe Fan, Chi-Ying Tsui: Low-Complexity Rotated QAM Demapper for the Iterative Receiver Targeting DVB-T2 Standard. VTC Fall 2012: 1-5
- 2011
- [j19]Hui Shao, X. Li, Chi-Ying Tsui: Low energy multi-stage level converter for sub-threshold logic. IET Computers & Digital Techniques 5(5): 375-385 (2011)
- [j18]Chao Lu, Chi-Ying Tsui, Wing-Hung Ki: Vibration Energy Scavenging System With Maximum Power Tracking for Micropower Applications. IEEE Trans. VLSI Syst. 19(11): 2109-2119 (2011)
- [c79]Zhiliang Qian, Chi-Ying Tsui: A thermal-aware application specific routing algorithm for Network-on-Chip design. ASP-DAC 2011: 449-454
- [c78]YouZhe Fan, James She, Chi-Ying Tsui: Efficient iterative receiver for LDPC coded wireless IPTV system. ICIP 2011: 953-956
- [c77]Denis Guangyin Chen, Amine Bermak, Chi-Ying Tsui: A low-complexity image compression algorithm for Address-Event Representation (AER) PWM image sensors. ISCAS 2011: 2825-2828
- [c76]Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui: A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources. VLSI-SoC 2011: 192-195
- [c75]Ying Fei Teh, Zhiliang Qian, Chi-Ying Tsui: A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme. VLSI-SoC 2011: 296-301
- [c74]Wing-Hung Ki, Yan Lu, Feng Su, Chi-Ying Tsui: Design and analysis of on-chip charge pumps for micro-power energy harvesting applications. VLSI-SoC 2011: 374-379
- 2010
- [j17]Jun Yin, Jun Yi, Matthew K. Law, Yunxiao Ling, Man Chiu Lee, Kwok Ping Ng, Bo Gao, Howard C. Luong, Amine Bermak, Mansun Chan, Wing-Hung Ki, Chi-Ying Tsui, Matthew Ming-Fai Yuen: A System-on-Chip EPC Gen-2 Passive UHF RFID Tag With Embedded Temperature Sensor. J. Solid-State Circuits 45(11): 2404-2420 (2010)
- [j16]Jie Jin, Chi-Ying Tsui: An Energy Efficient Layered Decoding Architecture for LDPC Decoder. IEEE Trans. VLSI Syst. 18(8): 1185-1195 (2010)
- [j15]Feng Liu, Chi-Ying Tsui, Ying Jun Zhang: Joint Routing and Sleep Scheduling for Lifetime Maximization of Wireless Sensor Networks. IEEE Transactions on Wireless Communications 9(7): 2258-2267 (2010)
- [c73]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki: Maximizing the harvested energy for micro-power applications through efficient MPPT and PMU design. ASP-DAC 2010: 75-80
- [c72]Yunxiao Ling, Jun Yi, Chi-Ying Tsui, Wing-Hung Ki: System level power optimizations for EPC RFID tags to improve sensitivity using load power shaping and operation scheduling. ISCAS 2010: 3012-3015
- [c71]Jun Yin, Jun Yi, Man Kay Law, Yunxiao Ling, Man Chiu Lee, Kwok Ping Ng, Bo Gao, Howard C. Luong, Amine Bermak, Mansun Chan, Wing-Hung Ki, Chi-Ying Tsui, Matthew Ming-Fai Yuen: A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor. ISSCC 2010: 308-309
- [c70]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki: A single inductor DIDO DC-DC converter for solar energy harvesting applications using band-band control. VLSI-SoC 2010: 167-172
2000 – 2009
- 2009
- [j14]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki: The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control. IEEE Trans. VLSI Syst. 17(8): 1138-1142 (2009)
- [c69]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki: An inductor-less MPPT design for light energy harvesting systems. ASP-DAC 2009: 101-102
- [c68]Hui Shao, Chi-Ying Tsui: Low energy level converter design for sub-Vth logics. ASP-DAC 2009: 107-108
- [c67]Ricky Yiu-kee Choi, Chi-Ying Tsui: A Low Energy Two-step Successive Approximation Algorithm for ADC Design. ISCAS 2009: 17-20
- [c66]Jie Jin, Chi-Ying Tsui: Improving the Hardware Utilization Efficiency of Partially Parallel LDPC Decoder with Scheduling and Sub-matrix Decomposition. ISCAS 2009: 2233-2236
- [c65]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki: A single inductor dual input dual output DC-DC converter with hybrid supplies for solar energy harvesting applications. ISLPED 2009: 69-74
- 2008
- [j13]Chi-Ying Tsui, Robert Yi-Ching Au, Ricky Yiu-kee Choi: Minimizing the dynamic and sub-threshold leakage power consumption using least leakage vector-assisted technology mapping. Integration 41(1): 76-86 (2008)
- [c64]Ngok-Man Sze, Wing-Hung Ki, Chi-Ying Tsui: Threshold Voltage Start-up Boost Converter for Sub-mA Applications. DELTA 2008: 338-341
- [c63]Ngok-Man Sze, Feng Su, Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui: Integrated single-inductor dual-input dual-output boost converter for energy harvesting applications. ISCAS 2008: 2218-2221
- [c62]Jun Yi, Feng Su, Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui: An energy-adaptive MPPT power management unit for micro-power vibration energy harvesting. ISCAS 2008: 2570-2573
- [c61]Jie Jin, Chi-Ying Tsui: A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes. ISLPED 2008: 253-258
- [c60]Ricky Yiu-kee Choi, Chi-Ying Tsui: A Low Energy Two-Step Successive Approximation Algorithm for ADC Design. ISQED 2008: 317-320
- 2007
- [j12]Jie Jin, Chi-Ying Tsui: Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. IEEE Trans. VLSI Syst. 15(10): 1172-1176 (2007)
- [c59]Lap-Fai Leung, Chi-Ying Tsui: Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands. DAC 2007: 128-131
- [c58]Chao Lu, Chi-Ying Tsui, Wing-Hung Ki: A Batteryless Vibration-based Energy Harvesting System for Ultra Low Power Ubiquitous Applications. ISCAS 2007: 1349-1352
- [c57]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki: An Inductor-less Micro Solar Power Management System Design for Energy Harvesting Applications. ISCAS 2007: 1353-1356
- [c56]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki: A micro power management system and maximum output power control for solar energy harvesting applications. ISLPED 2007: 298-303
- [c55]Chao Lu, Chi-Ying Tsui, Wing-Hung Ki: Vibration energy scavenging and management for ultra low power applications. ISLPED 2007: 316-321
- [c54]Wei-Feng He, Meng-Lian Zhao, Chi-Ying Tsui, Zhi-Gang Mao: A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation. VLSI Design 2007: 830-835
- [i1]Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu: Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling. CoRR abs/0710.4758 (2007)
- 2006
- [c53]Chi-Ying Tsui, Hui Shao, Wing-Hung Ki, Feng Su: Ultra-low voltage power management circuit and computation methodology for energy harvesting applications. ASP-DAC 2006: 96-97
- [c52]Yat-Hei Lam, Suet-Chui Koon, Wing-Hung Ki, Chi-Ying Tsui: Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors. ASP-DAC 2006: 102-103
- [c51]Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui: Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback. ASP-DAC 2006: 104-105
- [c50]Lap-Fai Leung, Chi-Ying Tsui: Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems. DAC 2006: 833-838
- [c49]
- [c48]Feng Liu, Chi-Ying Tsui: Energy-aware optimal workload allocation among the battery-powered devices to maximize the co-operation life time. ISCAS 2006
- [c47]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki: A charge based computation system and control strategy for energy harvesting applications. ISCAS 2006
- [c46]Feng Su, Wing-Hung Ki, Chi-Ying Tsui: High efficiency cross-coupled doubler with no reversion loss. ISCAS 2006
- [c45]Jie Jin, Chi-Ying Tsui: A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications. ISLPED 2006: 406-411
- [c44]
- 2005
- [c43]Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu: Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling. DATE 2005: 634-639
- [c42]Feng Liu, Chi-Ying Tsui: A Data Discarding Framework for Reducing the Energy Consumption of Viterbi Decoder in Decoding Broadcasted Wireless Multi-Resolution JPEG2000 Images. ESTImedia 2005: 21-26
- [c41]Wing-Hung Ki, Feng Su, Chi-Ying Tsui: Charge redistribution loss consideration in optimal charge pump design. ISCAS (2) 2005: 1895-1898
- [c40]Feng Su, Wing-Hung Ki, Chi-Ying Tsui: Gate control strategies for high efficiency charge pumps. ISCAS (2) 2005: 1907-1910
- [c39]Jin Jie, Chi-Ying Tsui, Wai Ho Mow: A threshold-based algorithm and VLSI architecture of a K-best lattice decoder for MIMO systems. ISCAS (4) 2005: 3359-3362
- 2004
- [c38]Yan Wang, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow: Power control of CDMA systems with successive interference cancellation using the knowledge of battery power capacity. ASP-DAC 2004: 125-130
- [c37]Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui: Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS process. ASP-DAC 2004: 539-540
- [c36]Martin Yeung-Kei Chui, Wing-Hung Ki, Chi-Ying Tsui: A dual--band switching digital controller for a buck converter. ASP-DAC 2004: 561-562
- [c35]Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki: Minimizing energy consumption of multiple-processors-core systems with simultaneous task allocation, scheduling and voltage assignment. ASP-DAC 2004: 647-652
- [c34]Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki: Minimizing energy consumption of hard real-time systems with simultaneous tasks scheduling and voltage assignment using statistical data. ASP-DAC 2004: 663-665
- [c33]Siu-Kei Wong, Chi-Ying Tsui: Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus. DATE 2004: 130-135
- [c32]Feng Liu, Chi-Ying Tsui: Adaptive spectrum-based variable bit truncation of discrete cosine transform (DCT) for energy-efficient wireless multimedia communication. ESTImedia 2004: 81-86
- [c31]Robert Yi-Ching Au, Chi-Ying Tsui: Least leakage vector assisted technology mapping for total power optimization. ISCAS (5) 2004: 145-148
- [c30]Siu-Kei Wong, Chi-Ying Tsui: Dynamic reconfigurable bus encoding scheme for reducing the energy consumption of deep sub-micron instruction bus. ISCAS (2) 2004: 321-324
- [c29]Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu: Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling. PATMOS 2004: 553-563
- 2003
- [c28]Chun Kit Hung, Mounir Hamdi, Chi-Ying Tsui: Design and implementation of high-speed arbiter for large scale VOQ crossbar switches. ISCAS (2) 2003: 308-311
- [c27]Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki: Simultaneous task allocation, scheduling and voltage assignment for multiple-processors-core systems using mixed integer nonlinear programming. ISCAS (5) 2003: 309-312
- [c26]Hing-mo Lam, Chi-Ying Tsui: High performance and low power completion detection circuit. ISCAS (5) 2003: 405-408
- [c25]Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok: Single-inductor dual-input dual-output switching converter for integrated battery charging and power regulation. ISCAS (3) 2003: 447-450
- 2002
- [c24]Jing Liu, Chun Kit Hung, Mounir Hamdi, Chi-Ying Tsui: Stable Round-Robin Scheduling Algorithms for High-Performance Input Queued Switches. Hot Interconnects 2002: 43-51
- [c23]Kwan-wai Wong, Chi-Ying Tsui, Roger S.-K. Cheng, Wai Ho Mow: A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels. ISCAS (3) 2002: 273-276
- [c22]Yan Wang, Hing Mo Lam, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow: Low complexity OFDM receiver using Log-FFT for coded OFDM system. ISCAS (3) 2002: 445-448
- [c21]Yan Wang, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow: Performance study of OFDM receiver using FFT based on log number system. VTC Spring 2002: 1257-1259
- 2001
- [j11]Oliver Yuk-Hang Leung, Chi-Ying Tsui, Roger S.-K. Cheng: Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage. IEEE Trans. VLSI Syst. 9(1): 34-41 (2001)
- [c20]Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok: A single-inductor dual-output integrated DC/DC boost converter for variable voltage scheduling. ASP-DAC 2001: 19-20
- [c19]Dongsheng Ma, Wing-Hung Ki, Philip K. T. Mok, Chi-Ying Tsui: Single-inductor multiple-output switching converters with bipolar outputs. ISCAS (3) 2001: 301-304
- 2000
- [j10]Zhong-Li He, Chi-Ying Tsui, Kai-Keung Chan, Ming L. Liou: Low-power VLSI design for motion estimation using adaptive pixel truncation. IEEE Trans. Circuits Syst. Video Techn. 10(5): 669-678 (2000)
- [j9]Chi-Ying Tsui, Roger S.-K. Cheng, Curtis Ling: Low Power Rake Receiver and Viterbi Decoder Design for CDMA Applications. Wireless Personal Communications 14(1): 49-64 (2000)
- [c18]Oliver Yuk-Hang Leung, Chi-Ying Tsui, Roger S. Cheng: VLSI implementation of rake receiver for IS-95 CDMA Testbed using FPGA. ASP-DAC 2000: 3-4
- [c17]Chi-Ying Tsui, Louis Chung-Yin Kwan, Chin-Tau Lea: VLSI implementation of a switch fabric for mixed ATM and IP traffic. ASP-DAC 2000: 5-6
1990 – 1999
- 1999
- [c16]Massoud Pedram, Chi-Ying Tsui, Qing Wu: An Integrated Battery-Hardware Model for Portable Electronics. ASP-DAC 1999: 109-
- [c15]Chun-hong Chen, Chi-Ying Tsui: Timing Optimization of Logic Network Using Gate Duplication. ASP-DAC 1999: 233-236
- [c14]Chi-Ying Tsui, Roger Shu-Kwan Cheng, Curtis Ling: Low power ACS unit design for the Viterbi decoder [CDMA wireless systems]. ISCAS (1) 1999: 137-140
- [c13]Wai-Kwong Lee, Chi-Ying Tsui: Finite state machine partitioning for low power. ISCAS (1) 1999: 306-309
- [c12]Chi Wai Yung, Hung Fai Fu, Chi-Ying Tsui, Roger S. Cheng, D. George: Unequal error protection for wireless transmission of MPEG audio. ISCAS (6) 1999: 342-345
- [c11]Oliver Yuk-Hang Leung, Chung-Wai Yue, Chi-Ying Tsui, Roger S. Cheng: Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage. ISLPED 1999: 36-41
- 1998
- [j8]Zhong-Li He, Ming L. Liou, Philip. C. H. Chan, Chi-Ying Tsui: Generic VLSI architecture for block-matching motion estimation algorithms. Int. J. Imaging Systems and Technology 9(4): 257-273 (1998)
- [j7]Chi-Ying Tsui, Massoud Pedram: Accurate and efficient power simulation strategy by compacting the input vector set. Integration 25(1): 37-52 (1998)
- [j6]Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram: Gate-level power estimation using tagged probabilistic simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1099-1107 (1998)
- [j5]Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain: Low-power state assignment targeting two- and multilevel logic implementations. IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1281-1291 (1998)
- [c10]Chun-hong Chen, Chi-Ying Tsui: Towards the capability of providing power-area-delay trade-off at the register transfer level. ISLPED 1998: 24-29
- 1997
- [c9]Chi-Ying Tsui, Kai-Keung Chan, Qing Wu, Chih-Shun Ding, Massoud Pedram: A Power Estimation Framework for Designing Low Power Portable Video Applications. DAC 1997: 421-424
- [c8]Zhong-Li He, Kai-Keung Chan, Chi-Ying Tsui, Ming L. Liou: Low power motion estimation design using adaptive pixel truncation. ISLPED 1997: 167-172
- 1996
- [j4]Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin: Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. IEEE Trans. VLSI Syst. 4(4): 495 (1996)
- [c7]Chi-Ying Tsui, Radu Marculescu, Diana Marculescu, Massoud Pedram: Improving the Efficiency of Power Simulators by Input Vector Compaction. DAC 1996: 165-168
- 1995
- [j3]Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin: Power estimation methods for sequential logic circuits. IEEE Trans. VLSI Syst. 3(3): 404-416 (1995)
- 1994
- [j2]Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain: Saving Power in the Control Path of Embedded Processors. IEEE Design & Test of Computers 11(4): 24-30 (1994)
- [j1]Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain: Power efficient technology decomposition and mapping under an extended power consumption model. IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1110-1122 (1994)
- [c6]Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain: Lower Power Architecture Design and Compilation Techniques for High-Performance Processors. COMPCON 1994: 489-498
- [c5]Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain: Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. DAC 1994: 18-23
- [c4]Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain: Low power state assignment targeting two-and multi-level logic implementations. ICCAD 1994: 82-87
- 1993
- [c3]Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain: Technology Decomposition and Mapping Targeting Low Power Dissipation. DAC 1993: 68-73
- [c2]Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain: Efficient estimation of dynamic power consumption under a real delay model. ICCAD 1993: 224-228
- 1992
- [c1]Iksoo Pyo, Ching-Long Su, Ing-Jer Huang, Kuo-Rueih Pan, Yong-Seon Koh, Chi-Ying Tsui, Hsu-Tsun Chen, Gino Cheng, Shihming Liu, Shiqun Wu, Alvin M. Despain: Application-Driven Design Automation for Microprocessor Design. DAC 1992: 512-517
Coauthor Index
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last updated on 2013-05-19 19:31 CEST by the dblp team