Yasumasa Tsukamoto

Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki: A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS. J. Solid-State Circuits 48(4): 917-923 (2013)

Koji Nii, Yasumasa Tsukamoto, Yuichiro Ishii, Makoto Yabuuchi, Hidehiro Fujiwara, Kazuyoshi Okamoto: A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. ATS 2012: 246-251

Yasumasa Tsukamoto, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Changhwan Shin, Tsu-Jae King Liu: Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application. ISQED 2012: 270-274

Takeshi Kida, Yasumasa Tsukamoto, Yuji Kihara: Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysis. ISQED 2012: 572-579

Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki: A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. ISSCC 2012: 236-238

Hidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii: A stable chip-ID generating physical uncloneable function using random address errors in SRAM. SoCC 2012: 143-147

Yuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yuji Kihara, K. Yanagisawa: A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. J. Solid-State Circuits 46(11): 2535-2544 (2011)

Yasumasa Tsukamoto, Takeshi Kida, T. Yamaki, Yuichiro Ishii, Koji Nii, Koji Tanaka, Shinji Tanaka, Yuji Kihara: Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs. CICC 2011: 1-4

Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Shigeki Tawa, Koji Maekawa, Motoshige Igarashi, Koji Nii: A dynamic body-biased SRAM with asymmetric halo implant MOSFETs. ISLPED 2011: 285-290

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yuji Kihara: A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias. ISSCC 2010: 356-357

Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara: Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. ICCAD 2005: 398-405

Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino: A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. ISCAS (1) 2005: 73-76

Masato Fujinaga, I. Tottori, Tatsuya Kunikiyo, Tetsuya Uchida, Norihiko Kotani, Yasumasa Tsukamoto: 3-D numerical modeling of thermal flow for insulating thin film using surface diffusion. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 631-638 (1995)