Shang-Wei Tu

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	2006
j1		Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou: RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2258-2264 (2006)
	2005
c3		Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. ISCAS (4) 2005: 4134-4137
	2004
c2		Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: Layout techniques for on-chip interconnect inductance reduction. ASP-DAC 2004: 269-273
c1		Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: RLC effects on worst-case switching pattern for on-chip buses. ISCAS (2) 2004: 945-948

Coauthor Index

1	Yao-Wen Chang	[j1] [c3] [c2] [c1]
2	Jing-Yang Jou	[j1] [c3] [c2] [c1]

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