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 | 2012 | |
|---|---|---|
| c5 |      | Jaynarayan T. Tudu, Deepak Malani, Virendra Singh: ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits. VDAT 2012: 172-179 |
| 2010 | ||
| c4 | | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara: Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. European Test Symposium 2010: 259 |
| c3 | | Aditi Kajala, Gayaprasad Sinsinwar, Rahul Raj Choudhary, Jaynarayan T. Tudu, Virendra Singh: On selection of state variables for delay test of identical functional units. EWDTS 2010: 200-203 |
| c2 | | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara: Graph theoretic approach for scan cell reordering to minimize peak shift power. ACM Great Lakes Symposium on VLSI 2010: 73-78 |
| 2009 | ||
| c1 | | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal: On Minimization of Peak Power for Scan Circuit during Test. European Test Symposium 2009: 25-30 |
| 1 | Vishwani D. Agrawal | |
| 2 | Rahul Raj Choudhary | |
| 3 | Hideo Fujiwara | |
| 4 | Aditi Kajala | |
| 5 | Erik Larsson | |
| 6 | Deepak Malani | |
| 7 | Virendra Singh | |
| 8 | Gayaprasad Sinsinwar |
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