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Raimund Ubar
2010 – today
- 2013
[j21]Ivo Fridolin, Deniss Karai, Sergei Kostin, Raimund Ubar: Accurate Dialysis Dose Evaluation and Extrapolation Algorithms During Online Optical Dialysis Monitoring. IEEE Trans. Biomed. Engineering 60(5): 1371-1377 (2013)- 2012
- [j20]Valerio Guarnieri, Giuseppe Di Guglielmo, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar: On the Reuse of TLM Mutation Analysis at RTL. J. Electronic Testing 28(4): 435-448 (2012)
- [j19]Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara: Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. J. Electronic Testing 28(4): 511-521 (2012)
- [c68]Raimund Ubar, Sergei Kostin, Jaan Raik: Multiple stuck-at-fault detection theorem. DDECS 2012: 236-241
- [c67]Raimund Ubar, Sergei Kostin, Jaan Raik: How to Prove that a Circuit is Fault-Free? DSD 2012: 427-430
- [c66]Urmas Repinski, Hanno Hantson, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Giuseppe Di Guglielmo, Graziano Pravadelli, Franco Fummi: Combining dynamic slicing and mutation operators for ESL correction. European Test Symposium 2012: 1-6
- [c65]Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik: Automated correction of design errors by edge redirection on High-Level Decision Diagrams. ISQED 2012: 686-693
- [e2]Jaan Raik, Viera Stopjaková, Heinrich Theodor Vierhaus, Witold A. Pleskacz, Raimund Ubar, Helena Kruus, Maksim Jenihhin (Eds.): IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012. IEEE 2012, ISBN 978-1-4673-1187-8
- 2011
- [j18]Eero Ivask, Sergei Devadze, Raimund Ubar: Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits. Scalable Computing: Practice and Experience 12(1) (2011)
- [c64]Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze: Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Asian Test Symposium 2011: 532-538
- [c63]Sergei Kostin, Raimund Ubar, Jaan Raik: Defect-oriented module-level fault diagnosis in digital circuits. DDECS 2011: 81-86
- [c62]Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik: Probabilistic equivalence checking based on high-level decision diagrams. DDECS 2011: 423-428
- [c61]Uljana Reinsalu, Jaan Raik, Raimund Ubar, Peeter Ellervee: Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations. DFT 2011: 164-170
- [c60]Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze: SoC and Board Modeling for Processor-Centric Board Testing. DSD 2011: 575-582
- [c59]Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara: Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. European Test Symposium 2011: 147-152
- [c58]Taavi Viilukas, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Samary Baranov: Automated test bench generation for high-level synthesis flow ABELITE. EWDTS 2011: 13-16
- [c57]Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik: Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams. HLDVT 2011: 83
- 2010
- [c56]Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Parallel X-fault simulation with critical path tracing technique. DATE 2010: 879-884
- [c55]Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko: Constraint-based test pattern generation at the Register-Transfer Level. DDECS 2010: 352-357
- [c54]Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. DELTA 2010: 14-19
- [c53]Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. DSD 2010: 658-663
- [c52]Maksim Jenihhin, Jaan Raik, Raimund Ubar, Tatjana Shchenova: An approach for PSL assertion coverage analysis with high-level decision diagrams. EWDTS 2010: 13-16
- [c51]Eero Ivask, Sergei Devadze, Raimund Ubar: Collaborative Distributed Fault Simulation for Digital Electronic Circuits. IDC 2010: 67-76
- [c50]Eero Ivask, Sergei Devadze, Raimund Ubar: Collaborative Distributed Computing in the Field of Digital Electronics Testing. BASYS 2010: 145-152
- [c49]Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman: Fault collapsing with linear complexity in digital circuits. ISCAS 2010: 653-656
- [c48]Heinz-Dietrich Wuttke, Raimund Ubar, Karsten Henke: Remote and Virtual Laboratories in Problem-Based Learning Scenarios. ISM 2010: 377-382
- [c47]Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman: Structural fault collapsing by superposition of BDDs for test generation in digital circuits. ISQED 2010: 250-257
- [i1]Y. A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, Raimund Ubar, Jaan Raik: Evolutionary Approach to Test Generation for Functional BIST. CoRR abs/1008.0063 (2010)
2000 – 2009
- 2009
- [j17]Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar: PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams. J. Electronic Testing 25(6): 289-300 (2009)
- [j16]Jaan Raik, Vineeth Govind, Raimund Ubar: Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. IET Computers & Digital Techniques 3(5): 476-486 (2009)
- [c46]Raimund Ubar, Sergei Kostin, Jaan Raik: Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems. DSD 2009: 229-232
- [c45]Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman: Structurally synthesized multiple input BDDs for simulation of digital circuits. ICECS 2009: 451-454
- [c44]Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar: Fast extended test access via JTAG and FPGAs. ITC 2009: 1-7
- 2008
- [j15]Tomas Bengtsson, Shashi Kumar, Raimund Ubar, Artur Jutman, Zebo Peng: Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols. IET Computers & Digital Techniques 2(6): 445-460 (2008)
- [j14]Jaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin: Mixed hierarchical-functional fault models for targeting sequential cores. Journal of Systems Architecture - Embedded Systems Design 54(3-4): 465-477 (2008)
- [j13]Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar: Hybrid BIST optimization using reseeding and test set compaction. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 254-262 (2008)
- [j12]Raimund Ubar, Sergei Kostin, Jaan Raik: Embedded fault diagnosis in digital systems with BIST. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 279-287 (2008)
- [c43]Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Parallel fault backtracing for calculation of fault coverage. ASP-DAC 2008: 667-672
- [c42]Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee: Code Coverage Analysis using High-Level Decision Diagrams. DDECS 2008: 201-206
- [c41]Eero Ivask, Jaan Raik, Raimund Ubar: Web-Based Framework for Parallel Distributed Test. DDECS 2008: 271-274
- [c40]Artur Jutman, Anton Tsertov, Raimund Ubar: Calculation of LFSR Seed and Polynomial Pair for BIST Applications. DDECS 2008: 275-278
- [c39]Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee: Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA 2008: 222-227
- [c38]Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz: Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. DSD 2008: 729-734
- [c37]Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar: Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. European Test Symposium 2008: 61-68
- [c36]Eero Ivask, Jaan Raik, Raimund Ubar: Distributed Approach for Genetic Test Generation in the Field of Digital Electronics. IDC 2008: 127-136
- 2007
- [j11]Peeter Ellervee, Jaan Raik, Kalle Tammemäe, Raimund Ubar: FPGA-based fault emulation of synchronous sequential circuits. IET Computers & Digital Techniques 1(2): 70-76 (2007)
- [j10]Raimund Ubar, Artur Jutman, Margus Kruus, Elmet Orasson, Sergei Devadze, Heinz-Dietrich Wuttke: Learning Digital Test and Diagnostics via Internet. iJOE 3(1) (2007)
- [c35]Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski: Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS 2007: 35-40
- [c34]Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar: Hybrid BIST Optimization Using Reseeding and Test Set Compaction. DSD 2007: 596-603
- [c33]Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evartson, Harri Lensen: Fault Diagnosis in Integrated Circuits with BIST. DSD 2007: 604-610
- [c32]Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus: Hierarchical Identification of Untestable Faults in Sequential Circuits. DSD 2007: 668-671
- [c31]Jaan Raik, Raimund Ubar, Vineeth Govind: Test Configurations for Diagnosing Faulty Links in NoC Switches. European Test Symposium 2007: 29-34
- [c30]Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. European Test Symposium 2007: 131-136
- [c29]Gert Jervan, Helena Kruus, Elmet Orasson, Raimund Ubar: Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems. SIES 2007: 71-77
- 2006
- [j9]Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin: Test Time Minimization for Hybrid BIST of Core-Based Systems. J. Comput. Sci. Technol. 21(6): 907-912 (2006)
- [c28]Jaan Raik, Raimund Ubar, Taavi Viilukas: High-Level Decision Diagram based Fault Models for Targeting FSMs. DSD 2006: 353-358
- [c27]Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng: Off-Line Testing of Delay Faults in NoC Interconnects. DSD 2006: 677-680
- [e1]Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubatova, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jiri Bucek (Eds.): Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006. IEEE Computer Society 2006, ISBN 1-4244-0185-2
- 2005
- [j8]Jaan Raik, Tanel Nõmmeots, Raimund Ubar: A New Testability Calculation Method to Guide RTL Test Generation. J. Electronic Testing 21(1): 71-82 (2005)
- [c26]Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar: Improved Fault Emulation for Synchronous Sequential Circuits. DSD 2005: 72-78
- [c25]Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz: Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. DSD 2005: 79-82
- [c24]Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov: An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. DSD 2005: 412-419
- [c23]Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman: Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. EDCC 2005: 332-344
- 2004
- [j7]Vladimir Hahanov, Raimund Ubar, Subhasish Mitra: Conference Reports. IEEE Design & Test of Computers 21(6): 594-595 (2004)
- [c22]Raimund Ubar, Maksim Jenihhin: Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting. DELTA 2004: 3-8
- [c21]Eero Ivask, Jaan Raik, Raimund Ubar, André Schneider: Web-Based Environment for Digital Electronics Test Tools. Virtual Enterprises and Collaborative Networks 2004: 435-442
- 2003
- [j6]Vladimir Hahanov, Raimund Ubar: Conference Reports. IEEE Design & Test of Computers 20(6): 103- (2003)
- [j5]Raimund Ubar: Design Error Diagnosis with Re-Synthesis in Combinational Circuits. J. Electronic Testing 19(1): 73-82 (2003)
- [c20]Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin: Test Time Minimization for Hybrid BIST of Core-Based Systems. Asian Test Symposium 2003: 318-325
- [c19]Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin: Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. DFT 2003: 225-
- [c18]Vladimir Hahanov, Raimund Ubar, Stanley Hyduke: Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. DSD 2003: 370-377
- 2002
- [j4]T. Cibáková, Mária Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Hierarchical test generation for combinational circuits with real defects coverage. Microelectronics Reliability 42(7): 1141-1149 (2002)
- [c17]André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová: Internet-Based Collaborative Test Generation with MOSCITO. DATE 2002: 221-226
- [c16]Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik: Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. DELTA 2002: 86-91
- [c15]André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng: Integrated Design and Test Generation Under Internet Based Environment MOSCITO. DSD 2002: 187-195
- [c14]Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus: A Hybrid BIST Architecture and Its Optimization for SoC Testing. ISQED 2002: 273-279
- 2001
- [j3]Mykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. Microelectronics Reliability 41(12): 2023-2040 (2001)
- [c13]Raimund Ubar, Artur Jutman, Zebo Peng: Timing simulation of digital circuits with binary decision diagrams. DATE 2001: 460-466
- [c12]Elmet Orasson, Rein Raidma, Raimund Ubar, Gert Jervan, Zebo Peng: Fast Test Cost Calculation for Hybrid BIST in Digital Systems. DSD 2001: 318-325
- [c11]Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED 2001: 365-371
- 2000
- [j2]Jaan Raik, Raimund Ubar: Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. J. Electronic Testing 16(3): 213-226 (2000)
- [c10]Adam Morawiec, Raimund Ubar, Jaan Raik: Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. DATE 2000: 743
- [c9]
- [c8]Raimund Ubar, Jaan Raik: Efficient Hierarchical Approach to Test Generation for Digital Systems. ISQED 2000: 189-196
1990 – 1999
- 1999
- [c7]Raimund Ubar, Jaan Raik, Adam Morawiec: Cycle-based Simulation with Decision Diagrams. DATE 1999: 454-458
- [c6]
- [c5]Raimund Ubar, Dominique Borrione: Design Error Diagnosis in Digital Circuits without Error Model. VLSI 1999: 281-292
- 1997
- [c4]Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Raimund Ubar: A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. ED&TC 1997: 560-565
- [c3]Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar: Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. DFT 1997: 212-217
- 1996
- [j1]Raimund Ubar: Test Synthesis with Alternative Graphs. IEEE Design & Test of Computers 13(1): 48-57 (1996)
- [c2]Raimund Ubar, Marina Brik: Multi-Level Test Generation and Fault Diagnosis for Finite State Machines. EDCC 1996: 264-282
- 1994
- [c1]
Coauthor Index
[j20] [j19] [c68] [c67] [c66] [c65] [e2] [c63] [c62] [c61] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c49] [c47] [i1] [j17] [j16] [c46] [c45] [j14] [j12] [c43] [c42] [c41] [c39] [c38] [c37] [c36] [j11] [c35] [c33] [c32] [c31] [c30] [c28] [j8] [c26] [c25] [c24] [c23] [c21] [j4] [c17] [c16] [j3] [c11] [j2] [c10] [c8] [c7] [c6] [c3]
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last updated on 2013-04-25 21:51 CEST by the dblp team