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Kunio Uchiyama
2010 – today
- 2012
[j7]Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tohru Nojiri, Kunio Uchiyama, Michitaka Kameyama: Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation. IEICE Transactions 95-C(12): 1872-1882 (2012)- 2011
- [j6]
- 2010
- [j5]
- [c6]Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, S. Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima: A 45nm 37.3GOPS/W heterogeneous multi-core SoC. ISSCC 2010: 100-101
2000 – 2009
- 2009
- [j4]
- 2008
- [c5]Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara: Software-cooperative power-efficient heterogeneous multi-core for media processing. ASP-DAC 2008: 736-741
- 2007
- [c4]Kunio Uchiyama: Power-Efficient Heterogeneous Multicore Technology for Digital Convergence. Asia-Pacific Computer Systems Architecture Conference 2007: 2-3
- 2005
- [j3]Kunio Uchiyama, Pradip Bose: Guest Editors' Introduction: Energy-Efficient Design. IEEE Micro 25(5): 6-9 (2005)
- [j2]Keisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai: Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction. Systems and Computers in Japan 36(6): 39-48 (2005)
- 2000
- [j1]Prasenjit Biswas, Atsushi Hasegawa, Srinivas Mandaville, Mark Debbage, Andy Sturges, Fumio Arakawa, Yasuhiko Saito, Kunio Uchiyama: SH-5: The 64-Bit SuperH Architecture. IEEE Micro 20(4): 28-39 (2000)
1990 – 1999
- 1998
- [c3]Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura: Design Methodology of a 200MHz Superscalar Microprocessor: SH-4. DAC 1998: 246-249
- 1994
- [c2]Tetsuhiko Okada, Susumu Narita, Osamu Nishii, Noriharu Hiratsuka, Nobuyuki Hayashi, Mitsuo Asai, Shinji Fujiwara, Mikiko Satoh, Junichi Nishimoto, Hirokazu Aoki, Kunio Uchiyama, Shigeru Matsuo, Hidehito Takewa, Kouji Yamada, Masahiro Kainaga, Norio Nakagawa, Masanobu Yamagami, Hiroshi Takeda, Tsuneo Funabashi: A PA-RISC Mikroprocessor PA/50L For Low-Cost Systems. COMPCON 1994: 47-52
- 1993
- [c1]Susumu Narita, Fumio Arakawa, Kunio Uchiyama, Ikuya Kawasaki: Design Methodology for GMICROTM/500 TRON Microprocessor. ICCD 1993: 253-257
Coauthor Index
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last updated on 2013-01-09 14:37 CET by the dblp team