Claudia Feregrino Uribe

Claudia Feregrino

	2013
j16		Miguel Morales-Sandoval, Claudia Feregrino Uribe, P. Kitsos, René Cumplido: Area/performance trade-off analysis of an FPGA digit-serial GF(2m)GF(2m) Montgomery multiplier based on LFSR. Computers & Electrical Engineering 39(2): 542-549 (2013)
j15		Jose Juan Garcia-Hernandez, Ramon Parra-Michel, Claudia Feregrino Uribe, René Cumplido: High payload data-hiding in audio signals based on a modified OFDM approach. Expert Syst. Appl. 40(8): 3055-3064 (2013)
	2012
j14		Pedro Aaron Hernandez-Avalos, Claudia Feregrino Uribe, René Cumplido: Watermarking using similarities based on fractal codification. Digital Signal Processing 22(2): 324-336 (2012)
j13		Alejandro Rojas, René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino, José Francisco Martínez Trinidad: Hardware-software platform for computing irreducible testors. Expert Syst. Appl. 39(2): 2203-2210 (2012)
j12		Claudia Feregrino, Miguel Arias, Kris Gaj, Viktor K. Prasanna, Marco D. Santambrogio, Ron Sass: Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10). Int. J. Reconfig. Comp. 2012 (2012)
c27		Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido: Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm. ISVLSI 2012: 63-68
	2011
j11		Miguel Morales-Sandoval, Claudia Feregrino Uribe, P. Kitsos: Bit-serial and digit-serial GF(2m)Montgomery multipliers using linear feedback shift registers. IET Computers & Digital Techniques 5(2): 86-94 (2011)
j10		Jose Juan Garcia-Hernandez, Claudia Feregrino Uribe, René Cumplido, Carolina Reta: On the Implementation of a Hardware Architecture for an Audio Data Hiding System. Signal Processing Systems 64(3): 457-468 (2011)
c26		Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval: Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. DSD 2011: 543-549
c25		René Cumplido, Claudia Feregrino Uribe, Jose Juan Garcia-Hernandez: Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware - Experiences on teaching and research. ReCoSoC 2011: 1-6
	2010
j9		Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval: Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard. Computers & Electrical Engineering 36(3): 565-577 (2010)
j8		Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo: A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter. Digital Signal Processing 20(6): 1733-1747 (2010)
j7		Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo: A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation. Journal of Circuits, Systems, and Computers 19(2): 425-433 (2010)
c24		Lázaro Bustio-Martínez, René Cumplido, José Hernández Palancar, Claudia Feregrino Uribe: On the Design of a Hardware-Software Architecture for Acceleration of SVM's Training Phase. MCPR 2010: 281-290
c23		Alejandro Mesa, Claudia Feregrino Uribe, René Cumplido, José Hernández Palancar: A Highly Parallel Algorithm for Frequent Itemset Mining. MCPR 2010: 291-300
	2009
j6		Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo: An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography. Computers & Electrical Engineering 35(1): 54-58 (2009)
j5		Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo: A versatile linear insertion sorter based on an FIFO scheme. Microelectronics Journal 40(12): 1705-1713 (2009)
c22		Hector Borrayo-Sandoval, Ramon Parra-Michel, Luis F. Gonzalez-Perez, Fernando Landeros Printzen, Claudia Feregrino Uribe: Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard. ReConFig 2009: 320-325
	2008
j4		Tomás Balderas-Contreras, René Cumplido, Claudia Feregrino Uribe: On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm. Computers & Electrical Engineering 34(6): 531-546 (2008)
j3		Raúl Rodríguez-Colín, Claudia Feregrino Uribe, Jose-Alberto Martinez Villanueva: Robust Watermarking Scheme Applied to Radiological Medical Images. IEICE Transactions 91-D(3): 862-864 (2008)
j2		Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval: Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description. IEICE Transactions 91-D(10): 2519-2523 (2008)
c21		Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo: A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. FPL 2008: 467-470
c20		Roberto Perez-Andrade, René Cumplido, Fernando Martin del Campo, Claudia Feregrino Uribe: A Versatile Linear Insertion Sorter Based on a FIFO Scheme. ISVLSI 2008: 357-362
c19		Jose Juan Garcia-Hernandez, Claudia Feregrino Uribe, René Cumplido: FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems. ReConFig 2008: 367-372
c18		Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval: FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. ReConFig 2008: 421-426
c17		Z. Jezabel Guzman Zavaleta, Claudia Feregrino Uribe, René Cumplido: A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation. ReConFig 2008: 444-449
	2007
c16		Alejandro Rojas, René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino Uribe, José Francisco Martínez Trinidad: FPGA-Based Architecture for Computing Testors. IDEAL 2007: 188-197
	2006
j1		Virgilio Zuñiga Grajeda, Claudia Feregrino Uribe, René Cumplido-Parra: Parallel Hardware/Software Architecture for the BWT and LZ77 Lossless Data Compression Algorithms. Computación y Sistemas 10(2) (2006)
c15		René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino: On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification. CIARP 2006: 665-673
c14		Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido: Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. ICCSA (3) 2006: 456-465
c13		Miguel Morales-Sandoval, Claudia Feregrino Uribe: GF(2m) Arithmetic Modules for Elliptic Curve Cryptography. ReConFig 2006: 176-183
c12		Roshan Mathew Duraisamy, Zoran A. Salcic, Miguel Morales-Sandoval, Claudia Feregrino Uribe: A Fast Elliptic Curve Based Key Agreement Protocol-on-Chip (PoC) for Securing Networked Embedded Systems. RTCSA 2006: 154-161
e1		Claudia Feregrino Uribe, Janeth Cruz Enríquez, J. Alejandro Díaz Méndez (Eds.): JIISIC'06 - V Jornadas Iberoamericanas de Ingeniería de Software e Ingeniería del Conocimiento, Memoria Técnica, Proceedings, Puebla, Pue. México, 1 al 3 de Febrero de 2006. 2006, isbn 970-94770-0-5
	2005
c11		Miguel Morales-Sandoval, Claudia Feregrino Uribe: A Hardware Architecture for Elliptic Curve Cryptography and Lossless Data Compression. CONIELECOMP 2005: 113-118
c10		Carlos Avendaño Pérez, Claudia Feregrino Uribe, Gonzalo Navarro: Approximate Searching on Compressed Text. CONIELECOMP 2005: 258-261
c9		José Francisco Martínez Trinidad, René Cumplido-Parra, Claudia Feregrino Uribe: An FPGA-based parallel sorting architecture for the Burrows Wheeler transform. ReConFig 2005
	2004
c8		Miguel Morales-Sandoval, Claudia Feregrino Uribe: On the Hardware Design of an Elliptic Curve Cryptosystem. ENC 2004: 64-70
	2003
c7		Claudia Feregrino Uribe: High Performance PPMC Compression Algorithm. ENC 2003: 135-
c6		Marco Aurelio Nuño-Maganda, Miguel O. Arias-Estrada, Claudia Feregrino Uribe: Three video applications using an FPGA based pyramid implementation: Tracking, Mosaics and Stabilization. FPT 2003: 336-339
	2001
c5		Claudia Feregrino Uribe, S. R. Jones: Optimisation of PPMC Model for Hardware Implementation. DSD 2001: 120-126
c4		Jose Luis Nunez, Claudia Feregrino, Simon Jones, Stephen Bateman: X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor. FPL 2001: 613-617
c3		Riad Stefo, Jose Luis Nunez, Claudia Feregrino, Sudipta Mahapatra, Simon Jones: FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding. FPL 2001: 643-647
	1999
c2		Jose Luis Nunez, Claudia Feregrino, Simon Jones, Stephen Bateman: The X-MatchLITE FPGA-Based Data Compressor. EUROMICRO 1999: 1126-1132
c1		Jose Luis Nunez, Claudia Feregrino, Stephen Bateman, Simon Jones: The X-MatchLITE FPGA-Based Data Compressor. FPGA 1999: 255

Coauthor Index

Colors in the list of coauthors

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