Prab Varma

List of publications from the DBLP Bibliography Server - FAQ
Other views: by type - by year (modern) - classic-C

Ask others: ACM DL/Guide -

- CSB - MetaPress - Google - Bing - Yahoo

	2012
c17		Prab Varma: Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network Validation. ATS 2012: 233-238
	2004
j3		Prab Varma: Verification evolution or industrial revolution? IEEE Design & Test of Computers 21(2): 168- (2004)
	2003
c16		Prab Varma: Design Verification Problems: Test To The Rescue? ITC 2003: 1292
	2001
c15		Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma: ATPG for Design Errors-Is It Possible? VTS 2001: 283-285
	2000
j2		Bechir Ayari, Prab Varma: Test Cycle Count Reduction in a Parallel Scan BIST Environment. J. Electronic Testing 16(5): 409-418 (2000)
	1998
c14		Bechir Ayari, Prab Varma: Test Cycle Count Reduction in a Parallel Scan BIST Environment. Asian Test Symposium 1998: 21-26
c13		Prab Varma: System Chip Test Challenges, Are There Solutions Today? (Panel). DAC 1998: 750-751
c12		Prab Varma, Sandeep Bhatia: A structured test re-use methodology for core-based system chips. ITC 1998: 294-302
c11		Prab Varma: System chip test: are we there yet? ITC 1998: 1144
	1997
c10		Sandeep Bhatia, Prab Varma: Test Compaction in a Parallel Access Scan Environment. Asian Test Symposium 1997: 300-305
	1996
c9		Sandeep Bhatia, Tushar Gheewala, Prab Varma: A Unifying Methodology for Intellectual Property and Custom Logic Testing. ITC 1996: 639-648
c8		Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma: Delay Fault Testing: How Robust are Our Models? VTS 1996: 502-503
	1995
c7		Prab Varma: Optimizing Product Profitability - The Test Way. ITC 1995: 922
	1994
j1		Prab Varma, Tushar Gheewala: The economics of scan-path design for testability. J. Electronic Testing 5(2-3): 179-193 (1994)
c6		Prab Varma: On Path-Delay Testing in a Standard Scan Environment. ITC 1994: 164-173
	1993
c5		Prab Varma, Tushar Gheewala: Delay Testing Using a Matrix of Accessible Storage. ITC 1993: 243-252
c4		Prab Varma: Scan DFT: Why More Can Cost Less. ITC 1993: 267
	1990
c3		Prab Varma: TDRC-a symbolic simulation based design for testability rules checker. ITC 1990: 1055-1064
	1987
c2		S. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter: A Fast Signature Simulation Tool for Built-In Self-Testing Circuits. DAC 1987: 17-25
	1984
c1		Prab Varma, Anthony P. Ambler, Keith Baker: An Analysis of the Economics of Self Test. ITC 1984: 20-30

Coauthor Index

1	Magdy S. Abadir	[c15]
2	Anthony P. Ambler	[c1]
3	Bechir Ayari	[j2] [c14]
4	Keith Baker	[c2] [c1]
5	Sandeep Bhatia	[c12] [c10] [c9]
6	Scott Davidson	[c15]
7	Tushar Gheewala	[c9] [j1] [c5]
8	Sandeep K. Gupta	[c8]
9	Vijay Nagasamy	[c15]
10	Slawomir Pilarski	[c8]
11	R. Porter	[c2]
12	Dhiraj K. Pradhan	[c15]
13	Sudhakar M. Reddy	[c8]
14	Jacob Savir	[c8]
15	S. B. Tan	[c2]
16	K. Totton	[c2]

Colors in the list of coauthors

Last update Mon May 20 21:44:54 2013 CET by the DBLP Team —

Data released under the ODC-BY 1.0 license — See also our legal information page